commit 34712c30639114dadc8e036b49ac8002c09ab2be
author Scott Michel <scottm@aero.org> Mon Mar 16 18:47:25 2009 +0000
committer Scott Michel <scottm@aero.org> Mon Mar 16 18:47:25 2009 +0000
tree 4b563a9a331b14307a65d5c161c5fbf38703929a
parent ba3172166d4b5e28c8f642543cfdf4fe9a0deffd

CellSPU:
Incorporate Tilmann's 128-bit operation patch. Evidently, it gets the
llvm-gcc bootstrap a bit further along.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67048 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/CellSPU/SPUInstrInfo.cpp

diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index 032eb14..8623f30 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -133,18 +133,22 @@
   case SPU::ORi128_f32:
   case SPU::ORi128_r16:
   case SPU::ORi128_r8:
+*/
   case SPU::ORi128_vec:
+/*
   case SPU::ORr64_i128:
   case SPU::ORf64_i128:
   case SPU::ORr32_i128:
   case SPU::ORf32_i128:
   case SPU::ORr16_i128:
   case SPU::ORr8_i128:
-  case SPU::ORvec_i128:
 */
+  case SPU::ORvec_i128:
 /*
   case SPU::ORr16_r32:
   case SPU::ORr8_r32:
+  case SPU::ORf32_r32:
+  case SPU::ORr32_f32:
   case SPU::ORr32_r16:
   case SPU::ORr32_r8:
   case SPU::ORr16_r64:
@@ -177,6 +181,7 @@
   case SPU::ORr16:
   case SPU::ORr32:
   case SPU::ORr64:
+  case SPU::ORr128:
   case SPU::ORf32:
   case SPU::ORf64:
     assert(MI.getNumOperands() == 3 &&