Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45680 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index e1ae37c..1e692c5 100644
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -431,7 +431,6 @@
bool LiveVariables::runOnMachineFunction(MachineFunction &mf) {
MF = &mf;
- const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
RegInfo = MF->getTarget().getRegisterInfo();
assert(RegInfo && "Target doesn't have register information?");
@@ -536,7 +535,7 @@
// Finally, if the last instruction in the block is a return, make sure to mark
// it as using all of the live-out values in the function.
- if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) {
+ if (!MBB->empty() && MBB->back().getDesc()->isReturn()) {
MachineInstr *Ret = &MBB->back();
for (MachineRegisterInfo::liveout_iterator
I = MF->getRegInfo().liveout_begin(),
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 49b7ef2..99bc222 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -252,13 +252,13 @@
/// instructions with variable number of operands).
MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
: TID(&tid), NumImplicitOps(0), Parent(0) {
- if (!NoImp && TID->ImplicitDefs)
- for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
+ if (!NoImp && TID->getImplicitDefs())
+ for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
NumImplicitOps++;
- if (!NoImp && TID->ImplicitUses)
- for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
+ if (!NoImp && TID->getImplicitUses())
+ for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
NumImplicitOps++;
- Operands.reserve(NumImplicitOps + TID->numOperands);
+ Operands.reserve(NumImplicitOps + TID->getNumOperands());
if (!NoImp)
addImplicitDefUseOperands();
// Make sure that we get added to a machine basicblock
@@ -273,12 +273,12 @@
: TID(&tid), NumImplicitOps(0), Parent(0) {
assert(MBB && "Cannot use inserting ctor with null basic block!");
if (TID->ImplicitDefs)
- for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
+ for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
NumImplicitOps++;
if (TID->ImplicitUses)
- for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
+ for (const unsigned *ImpUses = TID->getImplicitUses(); *ImpUses; ++ImpUses)
NumImplicitOps++;
- Operands.reserve(NumImplicitOps + TID->numOperands);
+ Operands.reserve(NumImplicitOps + TID->getNumOperands());
addImplicitDefUseOperands();
// Make sure that we get added to a machine basicblock
LeakDetector::addGarbageObject(this);
@@ -487,8 +487,8 @@
/// OperandComplete - Return true if it's illegal to add a new operand
///
bool MachineInstr::OperandsComplete() const {
- unsigned short NumOperands = TID->numOperands;
- if ((TID->Flags & M_VARIABLE_OPS) == 0 &&
+ unsigned short NumOperands = TID->getNumOperands();
+ if (TID->hasVariableOperands() == 0 &&
getNumOperands()-NumImplicitOps >= NumOperands)
return true; // Broken: we have all the operands of this instruction!
return false;
@@ -497,8 +497,8 @@
/// getNumExplicitOperands - Returns the number of non-implicit operands.
///
unsigned MachineInstr::getNumExplicitOperands() const {
- unsigned NumOperands = TID->numOperands;
- if ((TID->Flags & M_VARIABLE_OPS) == 0)
+ unsigned NumOperands = TID->getNumOperands();
+ if (TID->hasVariableOperands() == 0)
return NumOperands;
for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp
index d7c0a7b..0f2da0b 100644
--- a/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/lib/CodeGen/PrologEpilogInserter.cpp
@@ -262,7 +262,7 @@
// Add code to restore the callee-save registers in each exiting block.
for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI)
// If last instruction is a return instruction, add an epilogue.
- if (!FI->empty() && TII.isReturn(FI->back().getOpcode())) {
+ if (!FI->empty() && FI->back().getDesc()->isReturn()) {
MBB = FI;
I = MBB->end(); --I;
@@ -483,10 +483,9 @@
Fn.getTarget().getRegisterInfo()->emitPrologue(Fn);
// Add epilogue to restore the callee-save registers in each exiting block
- const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
// If last instruction is a return instruction, add an epilogue
- if (!I->empty() && TII.isReturn(I->back().getOpcode()))
+ if (!I->empty() && I->back().getDesc()->isReturn())
Fn.getTarget().getRegisterInfo()->emitEpilogue(Fn, *I);
}
}
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 3235f4a..499c2c7 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -52,8 +52,8 @@
unsigned ResNo = Use->getOperand(2).ResNo;
if (Def->isTargetOpcode()) {
const TargetInstrDescriptor &II = TII->get(Def->getTargetOpcode());
- if (ResNo >= II.numDefs &&
- II.ImplicitDefs[ResNo - II.numDefs] == Reg) {
+ if (ResNo >= II.getNumDefs() &&
+ II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
PhysReg = Reg;
const TargetRegisterClass *RC =
MRI->getPhysicalRegisterRegClass(Def->getValueType(ResNo), Reg);
@@ -149,7 +149,7 @@
if (MainNode->isTargetOpcode()) {
unsigned Opc = MainNode->getTargetOpcode();
const TargetInstrDescriptor &TID = TII->get(Opc);
- for (unsigned i = 0; i != TID.numOperands; ++i) {
+ for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
SU->isTwoAddress = true;
break;
@@ -166,8 +166,8 @@
for (unsigned n = 0, e = SU->FlaggedNodes.size(); n != e; ++n) {
SDNode *N = SU->FlaggedNodes[n];
if (N->isTargetOpcode() &&
- TII->getImplicitDefs(N->getTargetOpcode()) &&
- CountResults(N) > (unsigned)TII->getNumDefs(N->getTargetOpcode()))
+ TII->get(N->getTargetOpcode()).getImplicitDefs() &&
+ CountResults(N) > TII->get(N->getTargetOpcode()).getNumDefs())
SU->hasPhysRegDefs = true;
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
@@ -293,7 +293,7 @@
const TargetInstrInfo *TII,
const TargetInstrDescriptor *II,
unsigned Op) {
- if (Op >= II->numOperands) {
+ if (Op >= II->getNumOperands()) {
assert((II->Flags & M_VARIABLE_OPS)&& "Invalid operand # of instruction");
return NULL;
}
@@ -373,7 +373,7 @@
MachineInstr *MI,
const TargetInstrDescriptor &II,
DenseMap<SDOperand, unsigned> &VRBaseMap) {
- for (unsigned i = 0; i < II.numDefs; ++i) {
+ for (unsigned i = 0; i < II.getNumDefs(); ++i) {
// If the specific node value is only used by a CopyToReg and the dest reg
// is a vreg, use the CopyToReg'd destination register instead of creating
// a new vreg.
@@ -435,7 +435,7 @@
// Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap);
const TargetInstrDescriptor *TID = MI->getDesc();
- bool isOptDef = (IIOpNum < TID->numOperands)
+ bool isOptDef = (IIOpNum < TID->getNumOperands())
? (TID->OpInfo[IIOpNum].isOptionalDef()) : false;
MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
@@ -674,10 +674,11 @@
unsigned NumResults = CountResults(Node);
unsigned NodeOperands = CountOperands(Node);
unsigned NumMIOperands = NodeOperands + NumResults;
- bool HasPhysRegOuts = (NumResults > II.numDefs) && II.ImplicitDefs;
+ bool HasPhysRegOuts = (NumResults > II.getNumDefs()) &&
+ II.getImplicitDefs() != 0;
#ifndef NDEBUG
- assert((unsigned(II.numOperands) == NumMIOperands ||
- HasPhysRegOuts || (II.Flags & M_VARIABLE_OPS)) &&
+ assert((II.getNumOperands() == NumMIOperands ||
+ HasPhysRegOuts || II.hasVariableOperands()) &&
"#operands for dag node doesn't match .td file!");
#endif
@@ -692,7 +693,7 @@
// Emit all of the actual operands of this instruction, adding them to the
// instruction as appropriate.
for (unsigned i = 0; i != NodeOperands; ++i)
- AddOperand(MI, Node->getOperand(i), i+II.numDefs, &II, VRBaseMap);
+ AddOperand(MI, Node->getOperand(i), i+II.getNumDefs(), &II, VRBaseMap);
// Commute node if it has been determined to be profitable.
if (CommuteSet.count(Node)) {
@@ -719,8 +720,8 @@
// Additional results must be an physical register def.
if (HasPhysRegOuts) {
- for (unsigned i = II.numDefs; i < NumResults; ++i) {
- unsigned Reg = II.ImplicitDefs[i - II.numDefs];
+ for (unsigned i = II.getNumDefs(); i < NumResults; ++i) {
+ unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()];
if (Node->hasAnyUseOfValue(i))
EmitCopyFromReg(Node, i, InstanceNo, Reg, VRBaseMap);
}
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index fcc2b8a..846004e 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -148,7 +148,7 @@
if (!SU || !SU->Node) continue;
if (SU->isCommutable) {
unsigned Opc = SU->Node->getTargetOpcode();
- unsigned NumRes = TII->getNumDefs(Opc);
+ unsigned NumRes = TII->get(Opc).getNumDefs();
unsigned NumOps = CountOperands(SU->Node);
for (unsigned j = 0; j != NumOps; ++j) {
if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) == -1)
@@ -431,7 +431,7 @@
SUnit *NewSU = NewSUnit(N);
SUnitMap[N].push_back(NewSU);
const TargetInstrDescriptor *TID = &TII->get(N->getTargetOpcode());
- for (unsigned i = 0; i != TID->numOperands; ++i) {
+ for (unsigned i = 0; i != TID->getNumOperands(); ++i) {
if (TID->getOperandConstraint(i, TOI::TIED_TO) != -1) {
NewSU->isTwoAddress = true;
break;
@@ -623,8 +623,8 @@
const TargetInstrInfo *TII) {
const TargetInstrDescriptor &TID = TII->get(N->getTargetOpcode());
assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
- unsigned NumRes = TID.numDefs;
- for (const unsigned *ImpDef = TID.ImplicitDefs; *ImpDef; ++ImpDef) {
+ unsigned NumRes = TID.getNumDefs();
+ for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) {
if (Reg == *ImpDef)
break;
++NumRes;
@@ -1287,7 +1287,7 @@
bool BURegReductionPriorityQueue<SF>::canClobber(SUnit *SU, SUnit *Op) {
if (SU->isTwoAddress) {
unsigned Opc = SU->Node->getTargetOpcode();
- unsigned NumRes = TII->getNumDefs(Opc);
+ unsigned NumRes = TII->get(Opc).getNumDefs();
unsigned NumOps = ScheduleDAG::CountOperands(SU->Node);
for (unsigned i = 0; i != NumOps; ++i) {
if (TII->getOperandConstraint(Opc, i+NumRes, TOI::TIED_TO) != -1) {
@@ -1321,11 +1321,12 @@
const TargetInstrInfo *TII,
const MRegisterInfo *MRI) {
SDNode *N = SuccSU->Node;
- unsigned NumDefs = TII->getNumDefs(N->getTargetOpcode());
- const unsigned *ImpDefs = TII->getImplicitDefs(N->getTargetOpcode());
+ unsigned NumDefs = TII->get(N->getTargetOpcode()).getNumDefs();
+ const unsigned *ImpDefs = TII->get(N->getTargetOpcode()).getImplicitDefs();
if (!ImpDefs)
return false;
- const unsigned *SUImpDefs = TII->getImplicitDefs(SU->Node->getTargetOpcode());
+ const unsigned *SUImpDefs =
+ TII->get(SU->Node->getTargetOpcode()).getImplicitDefs();
if (!SUImpDefs)
return false;
for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
@@ -1361,7 +1362,7 @@
continue;
unsigned Opc = Node->getTargetOpcode();
- unsigned NumRes = TII->getNumDefs(Opc);
+ unsigned NumRes = TII->get(Opc).getNumDefs();
unsigned NumOps = ScheduleDAG::CountOperands(Node);
for (unsigned j = 0; j != NumOps; ++j) {
if (TII->getOperandConstraint(Opc, j+NumRes, TOI::TIED_TO) != -1) {
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 74a506c..2206515 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3602,7 +3602,7 @@
if (G) {
if (const TargetInstrInfo *TII = G->getTarget().getInstrInfo())
if (getOpcode()-ISD::BUILTIN_OP_END < TII->getNumOpcodes())
- return TII->getName(getOpcode()-ISD::BUILTIN_OP_END);
+ return TII->get(getOpcode()-ISD::BUILTIN_OP_END).getName();
TargetLowering &TLI = G->getTargetLoweringInfo();
const char *Name =
diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp
index 9eb3d7a..bc8d62e 100644
--- a/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -96,7 +96,7 @@
const TargetInstrDescriptor *TID = mi->getDesc();
bool FirstTied = true;
- for (unsigned si = 1, e = TID->numOperands; si < e; ++si) {
+ for (unsigned si = 1, e = TID->getNumOperands(); si < e; ++si) {
int ti = TID->getOperandConstraint(si, TOI::TIED_TO);
if (ti == -1)
continue;
@@ -176,7 +176,7 @@
// FIXME: This assumes there are no more operands which are tied
// to another register.
#ifndef NDEBUG
- for (unsigned i = si+1, e = TID->numOperands; i < e; ++i)
+ for (unsigned i = si+1, e = TID->getNumOperands(); i < e; ++i)
assert(TID->getOperandConstraint(i, TOI::TIED_TO) == -1);
#endif
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 967e292..a79a4a2 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -552,7 +552,7 @@
KillOps[Reg]->setIsKill(false);
KillOps[Reg] = NULL;
RegKills.reset(Reg);
- if (i < TID->numOperands &&
+ if (i < TID->getNumOperands() &&
TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
// Unless it's a two-address operand, this is the new kill.
MO.setIsKill();