Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45680 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index b291d19..fa52be8 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -63,7 +63,7 @@
return true;
case ARM::MOVr:
case ARM::tMOVr:
- assert(MI.getDesc()->numOperands >= 2 &&
+ assert(MI.getDesc()->getNumOperands() >= 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"Invalid ARM MOV instruction");
@@ -201,7 +201,7 @@
MachineInstr *MemMI = NULL;
unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
const TargetInstrDescriptor *TID = MI->getDesc();
- unsigned NumOps = TID->numOperands;
+ unsigned NumOps = TID->getNumOperands();
bool isLoad = TID->isSimpleLoad();
const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
const MachineOperand &Base = MI->getOperand(2);
@@ -897,7 +897,7 @@
case ARM::tBR_JTr: {
// These are jumptable branches, i.e. a branch followed by an inlined
// jumptable. The size is 4 + 4 * number of entries.
- unsigned NumOps = TID->numOperands;
+ unsigned NumOps = TID->getNumOperands();
MachineOperand JTOP =
MI->getOperand(NumOps - (TID->isPredicable() ? 3 : 2));
unsigned JTI = JTOP.getIndex();
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 152e2d1..29da83d 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -600,7 +600,7 @@
unsigned PredReg = 0;
ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
const TargetInstrDescriptor *TID = MBBI->getDesc();
- unsigned OffField = MBBI->getOperand(TID->numOperands-3).getImm();
+ unsigned OffField = MBBI->getOperand(TID->getNumOperands()-3).getImm();
int Offset = isAM2
? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;
if (isAM2) {