Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45680 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index 3c67d62..c4461a7 100644
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -444,7 +444,7 @@
if (Desc->TSFlags & X86II::REX_W)
REX |= 1 << 3;
- unsigned NumOps = Desc->numOperands;
+ unsigned NumOps = Desc->getNumOperands();
if (NumOps) {
bool isTwoAddr = NumOps > 1 &&
Desc->getOperandConstraint(1, TOI::TIED_TO) != -1;
@@ -584,7 +584,7 @@
MCE.emitByte(0x0F);
// If this is a two-address instruction, skip one of the register operands.
- unsigned NumOps = Desc->numOperands;
+ unsigned NumOps = Desc->getNumOperands();
unsigned CurOp = 0;
if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
CurOp++;
diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp
index 8c5d569..3d0d423 100644
--- a/lib/Target/X86/X86FloatingPoint.cpp
+++ b/lib/Target/X86/X86FloatingPoint.cpp
@@ -597,7 +597,7 @@
///
void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
- unsigned NumOps = MI->getDesc()->numOperands;
+ unsigned NumOps = MI->getDesc()->getNumOperands();
assert((NumOps == 5 || NumOps == 1) &&
"Can only handle fst* & ftst instructions!");
@@ -657,7 +657,7 @@
///
void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
- unsigned NumOps = MI->getDesc()->numOperands;
+ unsigned NumOps = MI->getDesc()->getNumOperands();
assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
// Is this the last use of the source register?
@@ -766,7 +766,7 @@
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
- unsigned NumOperands = MI->getDesc()->numOperands;
+ unsigned NumOperands = MI->getDesc()->getNumOperands();
assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
unsigned Dest = getFPReg(MI->getOperand(0));
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
@@ -864,7 +864,7 @@
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
- unsigned NumOperands = MI->getDesc()->numOperands;
+ unsigned NumOperands = MI->getDesc()->getNumOperands();
assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index eb455ca..cae382d 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -1640,7 +1640,7 @@
MIB.addImm(1).addReg(0).addImm(0);
// Loop over the rest of the ri operands, converting them over.
- unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2;
+ unsigned NumOps = MI->getDesc()->getNumOperands()-2;
for (unsigned i = 0; i != NumOps; ++i) {
MachineOperand &MO = MI->getOperand(i+2);
MIB = X86InstrAddOperand(MIB, MO);
@@ -1692,7 +1692,7 @@
SmallVector<MachineOperand,4> &MOs) const {
const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
bool isTwoAddrFold = false;
- unsigned NumOps = getNumOperands(MI->getOpcode());
+ unsigned NumOps = MI->getDesc()->getNumOperands();
bool isTwoAddr = NumOps > 1 &&
MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1;
@@ -1798,7 +1798,7 @@
return NULL;
SmallVector<MachineOperand,4> MOs;
- unsigned NumOps = getNumOperands(LoadMI->getOpcode());
+ unsigned NumOps = LoadMI->getDesc()->getNumOperands();
for (unsigned i = NumOps - 4; i != NumOps; ++i)
MOs.push_back(LoadMI->getOperand(i));
return foldMemoryOperand(MI, Ops[0], MOs);
@@ -1826,9 +1826,9 @@
unsigned OpNum = Ops[0];
unsigned Opc = MI->getOpcode();
- unsigned NumOps = getNumOperands(Opc);
+ unsigned NumOps = MI->getDesc()->getNumOperands();
bool isTwoAddr = NumOps > 1 &&
- getOperandConstraint(Opc, 1, TOI::TIED_TO) != -1;
+ MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1;
// Folding a memory location into the two-address part of a two-address
// instruction is different than folding it other places. It requires
@@ -2011,7 +2011,7 @@
// Emit the data processing instruction.
std::vector<MVT::ValueType> VTs;
const TargetRegisterClass *DstRC = 0;
- if (TID.numDefs > 0) {
+ if (TID.getNumDefs() > 0) {
const TargetOperandInfo &DstTOI = TID.OpInfo[0];
DstRC = DstTOI.isLookupPtrRegClass()
? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
@@ -2019,7 +2019,7 @@
}
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
MVT::ValueType VT = N->getValueType(i);
- if (VT != MVT::Other && i >= TID.numDefs)
+ if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
VTs.push_back(VT);
}
if (Load)