diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index b291d19..fa52be8 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -63,7 +63,7 @@
     return true;
   case ARM::MOVr:
   case ARM::tMOVr:
-    assert(MI.getDesc()->numOperands >= 2 &&
+    assert(MI.getDesc()->getNumOperands() >= 2 &&
            MI.getOperand(0).isRegister() &&
            MI.getOperand(1).isRegister() &&
            "Invalid ARM MOV instruction");
@@ -201,7 +201,7 @@
   MachineInstr *MemMI = NULL;
   unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
   const TargetInstrDescriptor *TID = MI->getDesc();
-  unsigned NumOps = TID->numOperands;
+  unsigned NumOps = TID->getNumOperands();
   bool isLoad = TID->isSimpleLoad();
   const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
   const MachineOperand &Base = MI->getOperand(2);
@@ -897,7 +897,7 @@
     case ARM::tBR_JTr: {
       // These are jumptable branches, i.e. a branch followed by an inlined
       // jumptable. The size is 4 + 4 * number of entries.
-      unsigned NumOps = TID->numOperands;
+      unsigned NumOps = TID->getNumOperands();
       MachineOperand JTOP =
         MI->getOperand(NumOps - (TID->isPredicable() ? 3 : 2));
       unsigned JTI = JTOP.getIndex();
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 152e2d1..29da83d 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -600,7 +600,7 @@
       unsigned PredReg = 0;
       ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
       const TargetInstrDescriptor *TID = MBBI->getDesc();
-      unsigned OffField = MBBI->getOperand(TID->numOperands-3).getImm();
+      unsigned OffField = MBBI->getOperand(TID->getNumOperands()-3).getImm();
       int Offset = isAM2
         ? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;
       if (isAM2) {
diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp
index cda5052..8896b35 100644
--- a/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/lib/Target/Mips/MipsInstrInfo.cpp
@@ -261,7 +261,7 @@
       unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
       const TargetInstrDescriptor &TID = get(Opc);
 
-      if (TID.numOperands == 3)
+      if (TID.getNumOperands() == 3)
         BuildMI(&MBB, TID).addReg(Cond[1].getReg())
                           .addReg(Cond[2].getReg())
                           .addMBB(TBB);
@@ -277,7 +277,7 @@
   unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
   const TargetInstrDescriptor &TID = get(Opc);
 
-  if (TID.numOperands == 3)
+  if (TID.getNumOperands() == 3)
     BuildMI(&MBB, TID).addReg(Cond[1].getReg())
                       .addReg(Cond[2].getReg())
                       .addMBB(TBB);
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 87c698b..7ab17bc 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -262,7 +262,7 @@
   
   // Find all return blocks, outputting a restore in each epilog.
   for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
-    if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) {
+    if (!BB->empty() && BB->back().getDesc()->isReturn()) {
       IP = BB->end(); --IP;
       
       // Skip over all terminator instructions, which are part of the return
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 7609e09..866c2bf 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -538,10 +538,9 @@
   bool RemovedAllMTVRSAVEs = true;
   // See if we can find and remove the MTVRSAVE instruction from all of the
   // epilog blocks.
-  const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
   for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
     // If last instruction is a return instruction, add an epilogue
-    if (!I->empty() && TII.isReturn(I->back().getOpcode())) {
+    if (!I->empty() && I->back().getDesc()->isReturn()) {
       bool FoundIt = false;
       for (MBBI = I->end(); MBBI != I->begin(); ) {
         --MBBI;
diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp
index ba56caa..5342dd1 100644
--- a/lib/Target/TargetInstrInfo.cpp
+++ b/lib/Target/TargetInstrInfo.cpp
@@ -19,7 +19,7 @@
 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
 /// dest operand. Returns -1 if there isn't one.
 int TargetInstrDescriptor::findTiedToSrcOperand(unsigned OpNum) const {
-  for (unsigned i = 0, e = numOperands; i != e; ++i) {
+  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     if (i == OpNum)
       continue;
     if (getOperandConstraint(i, TOI::TIED_TO) == (int)OpNum)
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index 3c67d62..c4461a7 100644
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -444,7 +444,7 @@
   if (Desc->TSFlags & X86II::REX_W)
     REX |= 1 << 3;
 
-  unsigned NumOps = Desc->numOperands;
+  unsigned NumOps = Desc->getNumOperands();
   if (NumOps) {
     bool isTwoAddr = NumOps > 1 &&
       Desc->getOperandConstraint(1, TOI::TIED_TO) != -1;
@@ -584,7 +584,7 @@
     MCE.emitByte(0x0F);
 
   // If this is a two-address instruction, skip one of the register operands.
-  unsigned NumOps = Desc->numOperands;
+  unsigned NumOps = Desc->getNumOperands();
   unsigned CurOp = 0;
   if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
     CurOp++;
diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp
index 8c5d569..3d0d423 100644
--- a/lib/Target/X86/X86FloatingPoint.cpp
+++ b/lib/Target/X86/X86FloatingPoint.cpp
@@ -597,7 +597,7 @@
 ///
 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
   MachineInstr *MI = I;
-  unsigned NumOps = MI->getDesc()->numOperands;
+  unsigned NumOps = MI->getDesc()->getNumOperands();
   assert((NumOps == 5 || NumOps == 1) &&
          "Can only handle fst* & ftst instructions!");
 
@@ -657,7 +657,7 @@
 ///
 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
   MachineInstr *MI = I;
-  unsigned NumOps = MI->getDesc()->numOperands;
+  unsigned NumOps = MI->getDesc()->getNumOperands();
   assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
 
   // Is this the last use of the source register?
@@ -766,7 +766,7 @@
   ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
   MachineInstr *MI = I;
 
-  unsigned NumOperands = MI->getDesc()->numOperands;
+  unsigned NumOperands = MI->getDesc()->getNumOperands();
   assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
   unsigned Dest = getFPReg(MI->getOperand(0));
   unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
@@ -864,7 +864,7 @@
   ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
   MachineInstr *MI = I;
 
-  unsigned NumOperands = MI->getDesc()->numOperands;
+  unsigned NumOperands = MI->getDesc()->getNumOperands();
   assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
   unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
   unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index eb455ca..cae382d 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -1640,7 +1640,7 @@
     MIB.addImm(1).addReg(0).addImm(0);
   
   // Loop over the rest of the ri operands, converting them over.
-  unsigned NumOps = TII.getNumOperands(MI->getOpcode())-2;
+  unsigned NumOps = MI->getDesc()->getNumOperands()-2;
   for (unsigned i = 0; i != NumOps; ++i) {
     MachineOperand &MO = MI->getOperand(i+2);
     MIB = X86InstrAddOperand(MIB, MO);
@@ -1692,7 +1692,7 @@
                                    SmallVector<MachineOperand,4> &MOs) const {
   const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
   bool isTwoAddrFold = false;
-  unsigned NumOps = getNumOperands(MI->getOpcode());
+  unsigned NumOps = MI->getDesc()->getNumOperands();
   bool isTwoAddr = NumOps > 1 &&
     MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1;
 
@@ -1798,7 +1798,7 @@
     return NULL;
 
   SmallVector<MachineOperand,4> MOs;
-  unsigned NumOps = getNumOperands(LoadMI->getOpcode());
+  unsigned NumOps = LoadMI->getDesc()->getNumOperands();
   for (unsigned i = NumOps - 4; i != NumOps; ++i)
     MOs.push_back(LoadMI->getOperand(i));
   return foldMemoryOperand(MI, Ops[0], MOs);
@@ -1826,9 +1826,9 @@
 
   unsigned OpNum = Ops[0];
   unsigned Opc = MI->getOpcode();
-  unsigned NumOps = getNumOperands(Opc);
+  unsigned NumOps = MI->getDesc()->getNumOperands();
   bool isTwoAddr = NumOps > 1 &&
-    getOperandConstraint(Opc, 1, TOI::TIED_TO) != -1;
+    MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1;
 
   // Folding a memory location into the two-address part of a two-address
   // instruction is different than folding it other places.  It requires
@@ -2011,7 +2011,7 @@
   // Emit the data processing instruction.
   std::vector<MVT::ValueType> VTs;
   const TargetRegisterClass *DstRC = 0;
-  if (TID.numDefs > 0) {
+  if (TID.getNumDefs() > 0) {
     const TargetOperandInfo &DstTOI = TID.OpInfo[0];
     DstRC = DstTOI.isLookupPtrRegClass()
       ? getPointerRegClass() : RI.getRegClass(DstTOI.RegClass);
@@ -2019,7 +2019,7 @@
   }
   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
     MVT::ValueType VT = N->getValueType(i);
-    if (VT != MVT::Other && i >= TID.numDefs)
+    if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
       VTs.push_back(VT);
   }
   if (Load)