Add encoding for VSUB and VCMP.
Fear not! I'm going to try a refactoring right now. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116359 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/MC/ARM/simple-fp-encoding.ll b/test/MC/ARM/simple-fp-encoding.ll
index 475a9c6..88bf8be 100644
--- a/test/MC/ARM/simple-fp-encoding.ll
+++ b/test/MC/ARM/simple-fp-encoding.ll
@@ -6,18 +6,50 @@
; assembly.
-define float @f1(float %a, float %b) nounwind readnone {
+define double @f1(double %a, double %b) nounwind readnone {
entry:
; CHECK: f1
+; CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee]
+ %add = fadd double %a, %b
+ ret double %add
+}
+
+define float @f2(float %a, float %b) nounwind readnone {
+entry:
+; CHECK: f2
; CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee]
%add = fadd float %a, %b
ret float %add
}
-define double @f2(double %a, double %b) nounwind readnone {
+define double @f3(double %a, double %b) nounwind readnone {
entry:
-; CHECK: f2
-; CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee]
- %add = fadd double %a, %b
- ret double %add
+; CHECK: f3
+; CHECK: vsub.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x71,0xee]
+ %sub = fsub double %a, %b
+ ret double %sub
+}
+
+define float @f4(float %a, float %b) nounwind readnone {
+entry:
+; CHECK: f4
+; CHECK: vsub.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x30,0xee]
+ %sub = fsub float %a, %b
+ ret float %sub
+}
+
+define i1 @f5(double %a, double %b) nounwind readnone {
+entry:
+; CHECK: f5
+; CHECK: vcmpe.f64 d17, d16 @ encoding: [0xe0,0x1b,0xf4,0xee]
+ %cmp = fcmp oeq double %a, %b
+ ret i1 %cmp
+}
+
+define i1 @f6(float %a, float %b) nounwind readnone {
+entry:
+; CHECK: f6
+; CHECK: vcmpe.f32 s1, s0 @ encoding: [0xc0,0x0a,0xf4,0xee]
+ %cmp = fcmp oeq float %a, %b
+ ret i1 %cmp
}