Rename MachineInstrInfo -> TargetInstrInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5272 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp
index fe5047b..20c60fe 100644
--- a/lib/CodeGen/InstrSched/InstrScheduling.cpp
+++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp
@@ -370,7 +370,7 @@
// Simplify access to the machine instruction info
//----------------------------------------------------------------------
- inline const MachineInstrInfo& getInstrInfo () const {
+ inline const TargetInstrInfo& getInstrInfo () const {
return schedInfo.getInstrInfo();
}
@@ -630,7 +630,7 @@
static void
RecordSchedule(MachineBasicBlock &MBB, const SchedulingManager& S)
{
- const MachineInstrInfo& mii = S.schedInfo.getInstrInfo();
+ const TargetInstrInfo& mii = S.schedInfo.getInstrInfo();
#ifndef NDEBUG
// Lets make sure we didn't lose any instructions, except possibly
@@ -1075,7 +1075,7 @@
return false;
// don't put a load-use dependence in the delay slot of a branch
- const MachineInstrInfo& mii = S.getInstrInfo();
+ const TargetInstrInfo& mii = S.getInstrInfo();
for (SchedGraphNode::const_iterator EI = node->beginInEdges();
EI != node->endInEdges(); ++EI)
@@ -1143,7 +1143,7 @@
SchedGraphNode* brNode,
vector<SchedGraphNode*>& sdelayNodeVec)
{
- const MachineInstrInfo& mii = S.getInstrInfo();
+ const TargetInstrInfo& mii = S.getInstrInfo();
unsigned ndelays =
mii.getNumDelaySlots(brNode->getOpCode());
@@ -1207,7 +1207,7 @@
SchedGraph* graph)
{
vector<SchedGraphNode*> nopNodeVec; // this will hold unused NOPs
- const MachineInstrInfo& mii = S.getInstrInfo();
+ const TargetInstrInfo& mii = S.getInstrInfo();
const MachineInstr* brInstr = node->getMachineInstr();
unsigned ndelays= mii.getNumDelaySlots(brInstr->getOpCode());
assert(ndelays > 0 && "Unnecessary call to replace NOPs");
@@ -1283,7 +1283,7 @@
ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB,
SchedGraph *graph)
{
- const MachineInstrInfo& mii = S.getInstrInfo();
+ const TargetInstrInfo& mii = S.getInstrInfo();
Instruction *termInstr = (Instruction*)MBB.getBasicBlock()->getTerminator();
MachineCodeForInstruction &termMvec=MachineCodeForInstruction::get(termInstr);
diff --git a/lib/CodeGen/InstrSched/SchedGraph.cpp b/lib/CodeGen/InstrSched/SchedGraph.cpp
index 7094068..0fcb22d 100644
--- a/lib/CodeGen/InstrSched/SchedGraph.cpp
+++ b/lib/CodeGen/InstrSched/SchedGraph.cpp
@@ -12,7 +12,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetRegInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Function.h"
#include "llvm/iOther.h"
#include "Support/StringExtras.h"
@@ -325,7 +325,7 @@
SchedGraph::addCDEdges(const TerminatorInst* term,
const TargetMachine& target)
{
- const MachineInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii = target.getInstrInfo();
MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
// Find the first branch instr in the sequence of machine instrs for term
@@ -434,7 +434,7 @@
SchedGraph::addMemEdges(const vector<SchedGraphNode*>& memNodeVec,
const TargetMachine& target)
{
- const MachineInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii = target.getInstrInfo();
// Instructions in memNodeVec are in execution order within the basic block,
// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
@@ -471,7 +471,7 @@
MachineBasicBlock& bbMvec,
const TargetMachine& target)
{
- const MachineInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii = target.getInstrInfo();
vector<SchedGraphNode*> callNodeVec;
// Find the call instruction nodes and put them in a vector.
@@ -675,7 +675,7 @@
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap)
{
- const MachineInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii = target.getInstrInfo();
MachineOpCode opCode = node->getOpCode();
@@ -732,7 +732,7 @@
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap)
{
- const MachineInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii = target.getInstrInfo();
// Build graph nodes for each VM instruction and gather def/use info.
// Do both those together in a single pass over all machine instructions.
diff --git a/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp b/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
index d7cb439..db9058f 100644
--- a/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
+++ b/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp
@@ -14,7 +14,7 @@
#include "llvm/CodeGen/InstrForest.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegInfo.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Constants.h"
#include "llvm/Function.h"
#include "llvm/DerivedTypes.h"
@@ -470,7 +470,7 @@
vector<MachineInstr*> loadConstVec;
MachineOpCode opCode = minstr->getOpCode();
- const MachineInstrInfo& instrInfo = target.getInstrInfo();
+ const TargetInstrInfo& instrInfo = target.getInstrInfo();
int resultPos = instrInfo.getResultPos(opCode);
int immedPos = instrInfo.getImmedConstantPos(opCode);
diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index d845f06..47bc8bd 100644
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -6,7 +6,7 @@
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/CFG.h"
#include "Support/DepthFirstIterator.h"
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index a2393eb..295d607 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -6,19 +6,19 @@
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/Value.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/MRegisterInfo.h"
using std::cerr;
// Global variable holding an array of descriptors for machine instructions.
// The actual object needs to be created separately for each target machine.
-// This variable is initialized and reset by class MachineInstrInfo.
+// This variable is initialized and reset by class TargetInstrInfo.
//
// FIXME: This should be a property of the target so that more than one target
// at a time can be active...
//
-extern const MachineInstrDescriptor *TargetInstrDescriptors;
+extern const TargetInstrDescriptor *TargetInstrDescriptors;
// Constructor for instructions with fixed #operands (nearly all)
MachineInstr::MachineInstr(MachineOpCode _opCode)
diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp
index ca243b8..57690e9 100644
--- a/lib/CodeGen/PHIElimination.cpp
+++ b/lib/CodeGen/PHIElimination.cpp
@@ -10,7 +10,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/LiveVariables.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
namespace {
diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp
index 0d57b10..21107a2 100644
--- a/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/lib/CodeGen/PrologEpilogInserter.cpp
@@ -16,7 +16,7 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetFrameInfo.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
namespace {
struct PEI : public MachineFunctionPass {
@@ -157,10 +157,10 @@
}
// Add code to restore the callee-save registers in each exiting block.
- const MachineInstrInfo &MII = Fn.getTarget().getInstrInfo();
+ const TargetInstrInfo &TII = Fn.getTarget().getInstrInfo();
for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI) {
// If last instruction is a return instruction, add an epilogue
- if (MII.isReturn(FI->back()->getOpcode())) {
+ if (TII.isReturn(FI->back()->getOpcode())) {
MBB = FI; I = MBB->end()-1;
for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) {
@@ -237,10 +237,10 @@
Fn.getTarget().getRegisterInfo()->emitPrologue(Fn);
// Add epilogue to restore the callee-save registers in each exiting block
- const MachineInstrInfo &MII = Fn.getTarget().getInstrInfo();
+ const TargetInstrInfo &TII = Fn.getTarget().getInstrInfo();
for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
// If last instruction is a return instruction, add an epilogue
- if (MII.isReturn(I->back()->getOpcode()))
+ if (TII.isReturn(I->back()->getOpcode()))
Fn.getTarget().getRegisterInfo()->emitEpilogue(Fn, *I);
}
}
diff --git a/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp b/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
index f8e4b4f..94e87b4 100644
--- a/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
+++ b/lib/CodeGen/RegAlloc/LiveRangeInfo.cpp
@@ -11,7 +11,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Function.h"
#include "Support/SetOperations.h"
using std::cerr;
diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
index 6f15818..b747127 100644
--- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
@@ -16,7 +16,7 @@
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetFrameInfo.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Function.h"
#include "llvm/Type.h"
#include "llvm/iOther.h"
diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index 89c6506..d6e273a 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -11,7 +11,7 @@
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/LiveVariables.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "Support/Statistic.h"
#include "Support/CommandLine.h"
@@ -442,11 +442,11 @@
MachineBasicBlock::iterator I = MBB.begin();
for (; I != MBB.end(); ++I) {
MachineInstr *MI = *I;
- const MachineInstrDescriptor &MID = TM->getInstrInfo().get(MI->getOpcode());
+ const TargetInstrDescriptor &TID = TM->getInstrInfo().get(MI->getOpcode());
// Loop over the implicit uses, making sure that they are at the head of the
// use order list, so they don't get reallocated.
- if (const unsigned *ImplicitUses = MID.ImplicitUses)
+ if (const unsigned *ImplicitUses = TID.ImplicitUses)
for (unsigned i = 0; ImplicitUses[i]; ++i)
MarkPhysRegRecentlyUsed(ImplicitUses[i]);
@@ -498,7 +498,7 @@
}
// Loop over the implicit defs, spilling them as well.
- if (const unsigned *ImplicitDefs = MID.ImplicitDefs)
+ if (const unsigned *ImplicitDefs = TID.ImplicitDefs)
for (unsigned i = 0; ImplicitDefs[i]; ++i) {
unsigned Reg = ImplicitDefs[i];
spillPhysReg(MBB, I, Reg);
@@ -571,9 +571,9 @@
}
// Rewind the iterator to point to the first flow control instruction...
- const MachineInstrInfo &MII = TM->getInstrInfo();
+ const TargetInstrInfo &TII = TM->getInstrInfo();
I = MBB.end()-1;
- while (I != MBB.begin() && MII.isTerminatorInstr((*(I-1))->getOpcode()))
+ while (I != MBB.begin() && TII.isTerminatorInstr((*(I-1))->getOpcode()))
--I;
// Spill all physical registers holding virtual registers now.
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index 104d042..6b95af8 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -12,7 +12,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "Support/Statistic.h"
#include <iostream>
@@ -150,7 +150,7 @@
// a preliminary pass that will invalidate any registers that
// are used by the instruction (including implicit uses)
unsigned Opcode = MI->getOpcode();
- const MachineInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode);
+ const TargetInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode);
if (const unsigned *Regs = Desc.ImplicitUses)
while (*Regs)
RegsUsed[*Regs++] = true;