Rename MachineInstrInfo -> TargetInstrInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5272 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index 104d042..6b95af8 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -12,7 +12,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/SSARegMap.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "Support/Statistic.h"
#include <iostream>
@@ -150,7 +150,7 @@
// a preliminary pass that will invalidate any registers that
// are used by the instruction (including implicit uses)
unsigned Opcode = MI->getOpcode();
- const MachineInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode);
+ const TargetInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode);
if (const unsigned *Regs = Desc.ImplicitUses)
while (*Regs)
RegsUsed[*Regs++] = true;