Rename MachineInstrInfo -> TargetInstrInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5272 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
index fe5047b..20c60fe 100644
--- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
+++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
@@ -370,7 +370,7 @@
// Simplify access to the machine instruction info
//----------------------------------------------------------------------
- inline const MachineInstrInfo& getInstrInfo () const {
+ inline const TargetInstrInfo& getInstrInfo () const {
return schedInfo.getInstrInfo();
}
@@ -630,7 +630,7 @@
static void
RecordSchedule(MachineBasicBlock &MBB, const SchedulingManager& S)
{
- const MachineInstrInfo& mii = S.schedInfo.getInstrInfo();
+ const TargetInstrInfo& mii = S.schedInfo.getInstrInfo();
#ifndef NDEBUG
// Lets make sure we didn't lose any instructions, except possibly
@@ -1075,7 +1075,7 @@
return false;
// don't put a load-use dependence in the delay slot of a branch
- const MachineInstrInfo& mii = S.getInstrInfo();
+ const TargetInstrInfo& mii = S.getInstrInfo();
for (SchedGraphNode::const_iterator EI = node->beginInEdges();
EI != node->endInEdges(); ++EI)
@@ -1143,7 +1143,7 @@
SchedGraphNode* brNode,
vector<SchedGraphNode*>& sdelayNodeVec)
{
- const MachineInstrInfo& mii = S.getInstrInfo();
+ const TargetInstrInfo& mii = S.getInstrInfo();
unsigned ndelays =
mii.getNumDelaySlots(brNode->getOpCode());
@@ -1207,7 +1207,7 @@
SchedGraph* graph)
{
vector<SchedGraphNode*> nopNodeVec; // this will hold unused NOPs
- const MachineInstrInfo& mii = S.getInstrInfo();
+ const TargetInstrInfo& mii = S.getInstrInfo();
const MachineInstr* brInstr = node->getMachineInstr();
unsigned ndelays= mii.getNumDelaySlots(brInstr->getOpCode());
assert(ndelays > 0 && "Unnecessary call to replace NOPs");
@@ -1283,7 +1283,7 @@
ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB,
SchedGraph *graph)
{
- const MachineInstrInfo& mii = S.getInstrInfo();
+ const TargetInstrInfo& mii = S.getInstrInfo();
Instruction *termInstr = (Instruction*)MBB.getBasicBlock()->getTerminator();
MachineCodeForInstruction &termMvec=MachineCodeForInstruction::get(termInstr);
diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
index 7094068..0fcb22d 100644
--- a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
+++ b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
@@ -12,7 +12,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetRegInfo.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Function.h"
#include "llvm/iOther.h"
#include "Support/StringExtras.h"
@@ -325,7 +325,7 @@
SchedGraph::addCDEdges(const TerminatorInst* term,
const TargetMachine& target)
{
- const MachineInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii = target.getInstrInfo();
MachineCodeForInstruction &termMvec = MachineCodeForInstruction::get(term);
// Find the first branch instr in the sequence of machine instrs for term
@@ -434,7 +434,7 @@
SchedGraph::addMemEdges(const vector<SchedGraphNode*>& memNodeVec,
const TargetMachine& target)
{
- const MachineInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii = target.getInstrInfo();
// Instructions in memNodeVec are in execution order within the basic block,
// so simply look at all pairs <memNodeVec[i], memNodeVec[j: j > i]>.
@@ -471,7 +471,7 @@
MachineBasicBlock& bbMvec,
const TargetMachine& target)
{
- const MachineInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii = target.getInstrInfo();
vector<SchedGraphNode*> callNodeVec;
// Find the call instruction nodes and put them in a vector.
@@ -675,7 +675,7 @@
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap)
{
- const MachineInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii = target.getInstrInfo();
MachineOpCode opCode = node->getOpCode();
@@ -732,7 +732,7 @@
RegToRefVecMap& regToRefVecMap,
ValueToDefVecMap& valueToDefVecMap)
{
- const MachineInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii = target.getInstrInfo();
// Build graph nodes for each VM instruction and gather def/use info.
// Do both those together in a single pass over all machine instructions.
diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
index d7cb439..db9058f 100644
--- a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
+++ b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp
@@ -14,7 +14,7 @@
#include "llvm/CodeGen/InstrForest.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegInfo.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Constants.h"
#include "llvm/Function.h"
#include "llvm/DerivedTypes.h"
@@ -470,7 +470,7 @@
vector<MachineInstr*> loadConstVec;
MachineOpCode opCode = minstr->getOpCode();
- const MachineInstrInfo& instrInfo = target.getInstrInfo();
+ const TargetInstrInfo& instrInfo = target.getInstrInfo();
int resultPos = instrInfo.getResultPos(opCode);
int immedPos = instrInfo.getImmedConstantPos(opCode);
diff --git a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
index f8e4b4f..94e87b4 100644
--- a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
+++ b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
@@ -11,7 +11,7 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Function.h"
#include "Support/SetOperations.h"
using std::cerr;
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index 6f15818..b747127 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -16,7 +16,7 @@
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetFrameInfo.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Function.h"
#include "llvm/Type.h"
#include "llvm/iOther.h"
diff --git a/lib/Target/SparcV9/SparcV9Instr.def b/lib/Target/SparcV9/SparcV9Instr.def
index 93613cb..af0fa88 100644
--- a/lib/Target/SparcV9/SparcV9Instr.def
+++ b/lib/Target/SparcV9/SparcV9Instr.def
@@ -35,7 +35,7 @@
// numDelaySlots (in cycles)
// latency (in cycles)
// instr sched class (defined above)
-// instr class flags (defined in MachineInstrInfo.h)
+// instr class flags (defined in TargetInstrInfo.h)
diff --git a/lib/Target/SparcV9/SparcV9InstrInfo.cpp b/lib/Target/SparcV9/SparcV9InstrInfo.cpp
index 9891cff..df4bbc3 100644
--- a/lib/Target/SparcV9/SparcV9InstrInfo.cpp
+++ b/lib/Target/SparcV9/SparcV9InstrInfo.cpp
@@ -321,14 +321,14 @@
// Information about individual instructions.
// Most information is stored in the SparcMachineInstrDesc array above.
// Other information is computed on demand, and most such functions
-// default to member functions in base class MachineInstrInfo.
+// default to member functions in base class TargetInstrInfo.
//---------------------------------------------------------------------------
/*ctor*/
UltraSparcInstrInfo::UltraSparcInstrInfo()
- : MachineInstrInfo(SparcMachineInstrDesc,
- /*descSize = */ NUM_TOTAL_OPCODES,
- /*numRealOpCodes = */ NUM_REAL_OPCODES)
+ : TargetInstrInfo(SparcMachineInstrDesc,
+ /*descSize = */ NUM_TOTAL_OPCODES,
+ /*numRealOpCodes = */ NUM_REAL_OPCODES)
{
InitializeMaxConstantsTable();
}
diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h
index e5eaa0f..793189a 100644
--- a/lib/Target/SparcV9/SparcV9Internals.h
+++ b/lib/Target/SparcV9/SparcV9Internals.h
@@ -41,7 +41,7 @@
//---------------------------------------------------------------------------
// enum SparcMachineOpCode.
-// const MachineInstrDescriptor SparcMachineInstrDesc[]
+// const TargetInstrDescriptor SparcMachineInstrDesc[]
//
// Purpose:
// Description of UltraSparc machine instructions.
@@ -62,7 +62,7 @@
// Array of machine instruction descriptions...
-extern const MachineInstrDescriptor SparcMachineInstrDesc[];
+extern const TargetInstrDescriptor SparcMachineInstrDesc[];
//---------------------------------------------------------------------------
@@ -72,10 +72,10 @@
// Information about individual instructions.
// Most information is stored in the SparcMachineInstrDesc array above.
// Other information is computed on demand, and most such functions
-// default to member functions in base class MachineInstrInfo.
+// default to member functions in base class TargetInstrInfo.
//---------------------------------------------------------------------------
-struct UltraSparcInstrInfo : public MachineInstrInfo {
+struct UltraSparcInstrInfo : public TargetInstrInfo {
UltraSparcInstrInfo();
//
@@ -733,7 +733,7 @@
public:
UltraSparc();
- virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
+ virtual const TargetInstrInfo &getInstrInfo() const { return instrInfo; }
virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; }
virtual const TargetRegInfo &getRegInfo() const { return regInfo; }
virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; }
diff --git a/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp b/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
index f255fb7..9cff89f 100644
--- a/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
+++ b/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
@@ -9,7 +9,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOptInfo.h"
#include "llvm/BasicBlock.h"
#include "llvm/Pass.h"
@@ -24,7 +24,7 @@
// Check if this instruction is in a delay slot of its predecessor.
if (BBI != mvec.begin())
{
- const MachineInstrInfo& mii = target.getInstrInfo();
+ const TargetInstrInfo& mii = target.getInstrInfo();
MachineInstr* predMI = *(BBI-1);
if (unsigned ndelay = mii.getNumDelaySlots(predMI->getOpCode()))
{
diff --git a/lib/Target/SparcV9/SparcV9PreSelection.cpp b/lib/Target/SparcV9/SparcV9PreSelection.cpp
index 2c3dcf2..7cd5b1d 100644
--- a/lib/Target/SparcV9/SparcV9PreSelection.cpp
+++ b/lib/Target/SparcV9/SparcV9PreSelection.cpp
@@ -10,7 +10,7 @@
#include "llvm/CodeGen/PreSelection.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Transforms/Scalar.h"
#include "llvm/Support/InstVisitor.h"
#include "llvm/Module.h"
diff --git a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
index be2cdfa..5859cb0 100644
--- a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
+++ b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
@@ -96,7 +96,7 @@
void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF)
{
const TargetMachine &TM = MF.getTarget();
- const MachineInstrInfo &MII = TM.getInstrInfo();
+ const TargetInstrInfo &MII = TM.getInstrInfo();
for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
MachineBasicBlock &MBB = *I;
diff --git a/lib/Target/SparcV9/SparcV9StackSlots.cpp b/lib/Target/SparcV9/SparcV9StackSlots.cpp
index 8f3a507..1ff54b9 100644
--- a/lib/Target/SparcV9/SparcV9StackSlots.cpp
+++ b/lib/Target/SparcV9/SparcV9StackSlots.cpp
@@ -8,16 +8,14 @@
#include "llvm/CodeGen/StackSlots.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/MachineInstrInfo.h"
#include "llvm/Constant.h"
#include "llvm/Function.h"
#include "llvm/DerivedTypes.h"
-#include "llvm/Pass.h"
-#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineFunctionInfo.h"
namespace {
- class StackSlots : public FunctionPass {
+ class StackSlots : public MachineFunctionPass {
const TargetMachine &Target;
public:
StackSlots(const TargetMachine &T) : Target(T) {}
@@ -30,12 +28,12 @@
AU.setPreservesCFG();
}
- bool runOnFunction(Function &F) {
+ bool runOnMachineFunction(MachineFunction &MF) {
const Type *PtrInt = PointerType::get(Type::IntTy);
unsigned Size = Target.getTargetData().getTypeSize(PtrInt);
Value *V = Constant::getNullValue(Type::IntTy);
- MachineFunction::get(&F).getInfo()->allocateLocalVar(V, 2*Size);
+ MF.getInfo()->allocateLocalVar(V, 2*Size);
return true;
}
};
diff --git a/lib/Target/SparcV9/SparcV9TargetMachine.cpp b/lib/Target/SparcV9/SparcV9TargetMachine.cpp
index e177910..81de95c 100644
--- a/lib/Target/SparcV9/SparcV9TargetMachine.cpp
+++ b/lib/Target/SparcV9/SparcV9TargetMachine.cpp
@@ -26,7 +26,7 @@
static const unsigned ImplicitRegUseList[] = { 0 }; /* not used yet */
// Build the MachineInstruction Description Array...
-const MachineInstrDescriptor SparcMachineInstrDesc[] = {
+const TargetInstrDescriptor SparcMachineInstrDesc[] = {
#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
{ OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
@@ -124,7 +124,7 @@
// Primary interface to machine description for the UltraSPARC.
// Primarily just initializes machine-dependent parameters in
// class TargetMachine, and creates machine-dependent subclasses
-// for classes such as MachineInstrInfo.
+// for classes such as TargetInstrInfo.
//
//---------------------------------------------------------------------------
diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp
index ae29c54..c329a81 100644
--- a/lib/Target/TargetInstrInfo.cpp
+++ b/lib/Target/TargetInstrInfo.cpp
@@ -3,7 +3,7 @@
//
//===----------------------------------------------------------------------===//
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Constant.h"
#include "llvm/DerivedTypes.h"
diff --git a/lib/Target/X86/FloatingPoint.cpp b/lib/Target/X86/FloatingPoint.cpp
index 7fdd97f..aac3fbc 100644
--- a/lib/Target/X86/FloatingPoint.cpp
+++ b/lib/Target/X86/FloatingPoint.cpp
@@ -10,7 +10,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/LiveVariables.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "Support/Statistic.h"
#include <algorithm>
diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp
index 43f2532..ee8318f 100644
--- a/lib/Target/X86/InstSelectSimple.cpp
+++ b/lib/Target/X86/InstSelectSimple.cpp
@@ -437,7 +437,7 @@
/// the current one.
///
void ISel::SelectPHINodes() {
- const MachineInstrInfo &MII = TM.getInstrInfo();
+ const TargetInstrInfo &TII = TM.getInstrInfo();
const Function &LF = *F->getFunction(); // The LLVM function...
for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
const BasicBlock *BB = I;
@@ -468,7 +468,7 @@
//
MachineBasicBlock::iterator PI = PredMBB->end();
while (PI != PredMBB->begin() &&
- MII.isTerminatorInstr((*(PI-1))->getOpcode()))
+ TII.isTerminatorInstr((*(PI-1))->getOpcode()))
--PI;
unsigned ValReg = getReg(PN->getIncomingValue(i), PredMBB, PI);
PhiMI->addRegOperand(ValReg);
diff --git a/lib/Target/X86/MachineCodeEmitter.cpp b/lib/Target/X86/MachineCodeEmitter.cpp
index 1e2ce9d..5721d4b 100644
--- a/lib/Target/X86/MachineCodeEmitter.cpp
+++ b/lib/Target/X86/MachineCodeEmitter.cpp
@@ -220,7 +220,7 @@
}
}
-unsigned sizeOfPtr (const MachineInstrDescriptor &Desc) {
+unsigned sizeOfPtr(const TargetInstrDescriptor &Desc) {
switch (Desc.TSFlags & X86II::ArgMask) {
case X86II::Arg8: return 1;
case X86II::Arg16: return 2;
@@ -236,7 +236,7 @@
void Emitter::emitInstruction(MachineInstr &MI) {
unsigned Opcode = MI.getOpcode();
- const MachineInstrDescriptor &Desc = II->get(Opcode);
+ const TargetInstrDescriptor &Desc = II->get(Opcode);
// Emit instruction prefixes if neccesary
if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
diff --git a/lib/Target/X86/Printer.cpp b/lib/Target/X86/Printer.cpp
index b71f3f2..95e8642 100644
--- a/lib/Target/X86/Printer.cpp
+++ b/lib/Target/X86/Printer.cpp
@@ -59,7 +59,7 @@
bool Printer::runOnMachineFunction(MachineFunction &MF) {
static unsigned BBNumber = 0;
const TargetMachine &TM = MF.getTarget();
- const MachineInstrInfo &MII = TM.getInstrInfo();
+ const TargetInstrInfo &TII = TM.getInstrInfo();
// Print out constants referenced by the function
printConstantPool(MF.getConstantPool(), TM.getTargetData());
@@ -80,7 +80,7 @@
II != E; ++II) {
// Print the assembly for the instruction.
O << "\t";
- MII.print(*II, O, TM);
+ TII.print(*II, O, TM);
}
}
@@ -136,7 +136,7 @@
}
}
-static const std::string sizePtr(const MachineInstrDescriptor &Desc) {
+static const std::string sizePtr(const TargetInstrDescriptor &Desc) {
switch (Desc.TSFlags & X86II::ArgMask) {
default: assert(0 && "Unknown arg size!");
case X86II::Arg8: return "BYTE PTR";
@@ -204,7 +204,7 @@
void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
const TargetMachine &TM) const {
unsigned Opcode = MI->getOpcode();
- const MachineInstrDescriptor &Desc = get(Opcode);
+ const TargetInstrDescriptor &Desc = get(Opcode);
switch (Desc.TSFlags & X86II::FormMask) {
case X86II::Pseudo:
diff --git a/lib/Target/X86/X86AsmPrinter.cpp b/lib/Target/X86/X86AsmPrinter.cpp
index b71f3f2..95e8642 100644
--- a/lib/Target/X86/X86AsmPrinter.cpp
+++ b/lib/Target/X86/X86AsmPrinter.cpp
@@ -59,7 +59,7 @@
bool Printer::runOnMachineFunction(MachineFunction &MF) {
static unsigned BBNumber = 0;
const TargetMachine &TM = MF.getTarget();
- const MachineInstrInfo &MII = TM.getInstrInfo();
+ const TargetInstrInfo &TII = TM.getInstrInfo();
// Print out constants referenced by the function
printConstantPool(MF.getConstantPool(), TM.getTargetData());
@@ -80,7 +80,7 @@
II != E; ++II) {
// Print the assembly for the instruction.
O << "\t";
- MII.print(*II, O, TM);
+ TII.print(*II, O, TM);
}
}
@@ -136,7 +136,7 @@
}
}
-static const std::string sizePtr(const MachineInstrDescriptor &Desc) {
+static const std::string sizePtr(const TargetInstrDescriptor &Desc) {
switch (Desc.TSFlags & X86II::ArgMask) {
default: assert(0 && "Unknown arg size!");
case X86II::Arg8: return "BYTE PTR";
@@ -204,7 +204,7 @@
void X86InstrInfo::print(const MachineInstr *MI, std::ostream &O,
const TargetMachine &TM) const {
unsigned Opcode = MI->getOpcode();
- const MachineInstrDescriptor &Desc = get(Opcode);
+ const TargetInstrDescriptor &Desc = get(Opcode);
switch (Desc.TSFlags & X86II::FormMask) {
case X86II::Pseudo:
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index 1e2ce9d..5721d4b 100644
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -220,7 +220,7 @@
}
}
-unsigned sizeOfPtr (const MachineInstrDescriptor &Desc) {
+unsigned sizeOfPtr(const TargetInstrDescriptor &Desc) {
switch (Desc.TSFlags & X86II::ArgMask) {
case X86II::Arg8: return 1;
case X86II::Arg16: return 2;
@@ -236,7 +236,7 @@
void Emitter::emitInstruction(MachineInstr &MI) {
unsigned Opcode = MI.getOpcode();
- const MachineInstrDescriptor &Desc = II->get(Opcode);
+ const TargetInstrDescriptor &Desc = II->get(Opcode);
// Emit instruction prefixes if neccesary
if (Desc.TSFlags & X86II::OpSize) MCE.emitByte(0x66);// Operand size...
diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp
index 7fdd97f..aac3fbc 100644
--- a/lib/Target/X86/X86FloatingPoint.cpp
+++ b/lib/Target/X86/X86FloatingPoint.cpp
@@ -10,7 +10,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/LiveVariables.h"
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "Support/Statistic.h"
#include <algorithm>
diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp
index 43f2532..ee8318f 100644
--- a/lib/Target/X86/X86ISelSimple.cpp
+++ b/lib/Target/X86/X86ISelSimple.cpp
@@ -437,7 +437,7 @@
/// the current one.
///
void ISel::SelectPHINodes() {
- const MachineInstrInfo &MII = TM.getInstrInfo();
+ const TargetInstrInfo &TII = TM.getInstrInfo();
const Function &LF = *F->getFunction(); // The LLVM function...
for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
const BasicBlock *BB = I;
@@ -468,7 +468,7 @@
//
MachineBasicBlock::iterator PI = PredMBB->end();
while (PI != PredMBB->begin() &&
- MII.isTerminatorInstr((*(PI-1))->getOpcode()))
+ TII.isTerminatorInstr((*(PI-1))->getOpcode()))
--PI;
unsigned ValReg = getReg(PN->getIncomingValue(i), PredMBB, PI);
PhiMI->addRegOperand(ValReg);
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 813d983..6b2fd64 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -1,6 +1,6 @@
//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
//
-// This file contains the X86 implementation of the MachineInstrInfo class.
+// This file contains the X86 implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
@@ -17,7 +17,7 @@
// X86Insts - Turn the InstrInfo.def file into a bunch of instruction
// descriptors
//
-static const MachineInstrDescriptor X86Insts[] = {
+static const TargetInstrDescriptor X86Insts[] = {
#define I(ENUM, NAME, BASEOPCODE, FLAGS, TSFLAGS, IMPUSES, IMPDEFS) \
{ NAME, \
-1, /* Always vararg */ \
@@ -35,7 +35,7 @@
};
X86InstrInfo::X86InstrInfo()
- : MachineInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
+ : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) {
}
diff --git a/lib/Target/X86/X86InstrInfo.def b/lib/Target/X86/X86InstrInfo.def
index 8528932..9d45d3b 100644
--- a/lib/Target/X86/X86InstrInfo.def
+++ b/lib/Target/X86/X86InstrInfo.def
@@ -51,7 +51,7 @@
// #2: Opcode name, as used by the gnu assembler
// #3: The base opcode for the instruction
// #4: Instruction Flags - This should be a field or'd together that contains
-// constants from the MachineInstrInfo.h file.
+// constants from the TargetInstrInfo.h file.
// #5: Target Specific Flags - Another bitfield containing X86 specific flags
// that we are interested in for each instruction. These should be flags
// defined in X86InstrInfo.h in the X86II namespace.
diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index 022c2d1..593fc0e 100644
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -1,13 +1,13 @@
//===- X86InstructionInfo.h - X86 Instruction Information ---------*-C++-*-===//
//
-// This file contains the X86 implementation of the MachineInstrInfo class.
+// This file contains the X86 implementation of the TargetInstrInfo class.
//
//===----------------------------------------------------------------------===//
#ifndef X86INSTRUCTIONINFO_H
#define X86INSTRUCTIONINFO_H
-#include "llvm/Target/MachineInstrInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "X86RegisterInfo.h"
/// X86II - This namespace holds all of the target specific flags that
@@ -137,12 +137,12 @@
};
}
-class X86InstrInfo : public MachineInstrInfo {
+class X86InstrInfo : public TargetInstrInfo {
const X86RegisterInfo RI;
public:
X86InstrInfo();
- /// getRegisterInfo - MachineInstrInfo is a superset of MRegister info. As
+ /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method).
///