commit 350c00843bad22c5391e33e9e39a78d5d0983c8c
author Benjamin Kramer <benny.kra@googlemail.com> Wed Nov 28 20:55:10 2012 +0000
committer Benjamin Kramer <benny.kra@googlemail.com> Wed Nov 28 20:55:10 2012 +0000
tree 1b85e673c4414ebeaed6c45c820483fb3ecf4e78
parent 1ead68d769f27f6d68d4aaeffe4199fa2cacbc95

ARM: Implement CanLowerReturn so large vectors get expanded into sret.

Fixes 14337.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168809 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMISelLowering.h

diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h
index 8bf803e..9cbf866 100644
--- a/lib/Target/ARM/ARMISelLowering.h
+++ b/lib/Target/ARM/ARMISelLowering.h
@@ -495,6 +495,12 @@
                                     const SmallVectorImpl<SDValue> &OutVals,
                                     const SmallVectorImpl<ISD::InputArg> &Ins,
                                            SelectionDAG& DAG) const;
+
+    virtual bool CanLowerReturn(CallingConv::ID CallConv,
+                                MachineFunction &MF, bool isVarArg,
+                                const SmallVectorImpl<ISD::OutputArg> &Outs,
+                                LLVMContext &Context) const;
+
     virtual SDValue
       LowerReturn(SDValue Chain,
                   CallingConv::ID CallConv, bool isVarArg,