commit 357be5e4ae712eae73d5985c2f6b91baa8bc4271
author Che-Liang Chiou <clchiou@gmail.com> Sat Apr 02 08:51:39 2011 +0000
committer Che-Liang Chiou <clchiou@gmail.com> Sat Apr 02 08:51:39 2011 +0000
tree 78f5b3212a6ca4329fb030a25c237bcf996d39af
parent eda0fe8d58b0aaff5f18e7f13edfda3022384e70

ptx: support setp's 4-operand format

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128767 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PTX/PTXInstrInfo.cpp

diff --git a/lib/Target/PTX/PTXInstrInfo.cpp b/lib/Target/PTX/PTXInstrInfo.cpp
index e8675f2..a12a6d0 100644
--- a/lib/Target/PTX/PTXInstrInfo.cpp
+++ b/lib/Target/PTX/PTXInstrInfo.cpp
@@ -130,42 +130,37 @@
 bool PTXInstrInfo::
 SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
                   const SmallVectorImpl<MachineOperand> &Pred2) const {
-  // TODO Implement SubsumesPredicate
-  // Returns true if the first specified predicate subsumes the second,
-  // e.g. GE subsumes GT.
-  return false;
+  const MachineOperand &PredReg1 = Pred1[0];
+  const MachineOperand &PredReg2 = Pred2[0];
+  if (PredReg1.getReg() != PredReg2.getReg())
+    return false;
+
+  const MachineOperand &PredOp1 = Pred1[1];
+  const MachineOperand &PredOp2 = Pred2[1];
+  if (PredOp1.getImm() != PredOp2.getImm())
+    return false;
+
+  return true;
 }
 
 bool PTXInstrInfo::
 DefinesPredicate(MachineInstr *MI,
                  std::vector<MachineOperand> &Pred) const {
-  // TODO Implement DefinesPredicate
-  // If the specified instruction defines any predicate or condition code
-  // register(s) used for predication, returns true as well as the definition
-  // predicate(s) by reference.
+  // If an instruction sets a predicate register, it defines a predicate.
 
-  switch (MI->getOpcode()) {
-  default:
+  // TODO supprot 5-operand format of setp instruction
+
+  if (MI->getNumOperands() < 1)
     return false;
-  case PTX::SETPEQu32rr:
-  case PTX::SETPEQu32ri:
-  case PTX::SETPNEu32rr:
-  case PTX::SETPNEu32ri:
-  case PTX::SETPLTu32rr:
-  case PTX::SETPLTu32ri:
-  case PTX::SETPLEu32rr:
-  case PTX::SETPLEu32ri:
-  case PTX::SETPGTu32rr:
-  case PTX::SETPGTu32ri:
-  case PTX::SETPGEu32rr:
-  case PTX::SETPGEu32ri: {
-    const MachineOperand &MO = MI->getOperand(0);
-    assert(MO.isReg() && RI.getRegClass(MO.getReg()) == &PTX::PredsRegClass);
-    Pred.push_back(MO);
-    Pred.push_back(MachineOperand::CreateImm(PTX::PRED_NORMAL));
-    return true;
-  }
-  }
+
+  const MachineOperand &MO = MI->getOperand(0);
+
+  if (!MO.isReg() || RI.getRegClass(MO.getReg()) != &PTX::PredsRegClass)
+    return false;
+
+  Pred.push_back(MO);
+  Pred.push_back(MachineOperand::CreateImm(PTX::PRED_NORMAL));
+  return true;
 }
 
 // branch support