Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.
Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0
If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
This is work in progress, not yet enabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 87d75dd..4d3417f 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -100,36 +100,15 @@
}
unsigned VirtRegMap::getRegAllocPref(unsigned virtReg) {
- std::pair<MachineRegisterInfo::RegAllocHintType, unsigned> Hint =
- MRI->getRegAllocationHint(virtReg);
- switch (Hint.first) {
- default: assert(0);
- case MachineRegisterInfo::RA_None:
- return 0;
- case MachineRegisterInfo::RA_Preference:
- if (TargetRegisterInfo::isPhysicalRegister(Hint.second))
- return Hint.second;
- if (hasPhys(Hint.second))
- return getPhys(Hint.second);
- case MachineRegisterInfo::RA_PairEven: {
- unsigned physReg = Hint.second;
- if (TargetRegisterInfo::isPhysicalRegister(physReg))
- return TRI->getRegisterPairEven(*MF, physReg);
- else if (hasPhys(physReg))
- return TRI->getRegisterPairEven(*MF, getPhys(physReg));
- return 0;
- }
- case MachineRegisterInfo::RA_PairOdd: {
- unsigned physReg = Hint.second;
- if (TargetRegisterInfo::isPhysicalRegister(physReg))
- return TRI->getRegisterPairOdd(*MF, physReg);
- else if (hasPhys(physReg))
- return TRI->getRegisterPairOdd(*MF, getPhys(physReg));
- return 0;
- }
- }
- // Shouldn't reach here.
- return 0;
+ std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(virtReg);
+ unsigned physReg = Hint.second;
+ if (physReg &&
+ TargetRegisterInfo::isVirtualRegister(physReg) && hasPhys(physReg))
+ physReg = getPhys(physReg);
+ if (Hint.first == 0)
+ return (physReg && TargetRegisterInfo::isPhysicalRegister(physReg))
+ ? physReg : 0;
+ return TRI->ResolveRegAllocHint(Hint.first, physReg, *MF);
}
int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {