Extend changes from r139986 to produce 256-bit AVX minps/minpd/maxps/maxpd.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140140 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index a570cd1..c21b1dc 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -12567,9 +12567,12 @@
   // instructions match the semantics of the common C idiom x<y?x:y but not
   // x<=y?x:y, because of how they handle negative zero (which can be
   // ignored in unsafe-math mode).
-  if (Subtarget->hasXMMInt() && Cond.getOpcode() == ISD::SETCC &&
-      (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64 ||
-       LHS.getValueType() == MVT::v4f32 || LHS.getValueType() == MVT::v2f64)) {
+  if (Cond.getOpcode() == ISD::SETCC &&
+      ((Subtarget->hasXMMInt() &&
+        (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::v4f32 || 
+         LHS.getValueType() == MVT::f64 || LHS.getValueType() == MVT::v2f64)) ||
+       (Subtarget->hasAVX() &&
+        (LHS.getValueType() == MVT::v8f32 || LHS.getValueType() == MVT::v4f64)))) {
     ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
 
     unsigned Opcode = 0;