ldmxcsr and stmxcsr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27506 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index f279c7b..c2dbeb5 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -1538,9 +1538,13 @@
def SFENCE : I<0xAE, MRM7m, (ops),
"sfence", []>, TB, Requires<[HasSSE1]>;
-// Load MXCSR register
+// MXCSR register
def LDMXCSR : I<0xAE, MRM2m, (ops i32mem:$src),
- "ldmxcsr {$src|$src}", []>, TB, Requires<[HasSSE1]>;
+ "ldmxcsr $src",
+ [(int_x86_sse_ldmxcsr addr:$src)]>, TB, Requires<[HasSSE1]>;
+def STMXCSR : I<0xAE, MRM3m, (ops i32mem:$dst),
+ "stmxcsr $dst",
+ [(int_x86_sse_stmxcsr addr:$dst)]>, TB, Requires<[HasSSE1]>;
//===----------------------------------------------------------------------===//
// Alias Instructions