No more noResults.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86InstrFPStack.td b/lib/Target/X86/X86InstrFPStack.td
index 3ef1cde6f..d4798f2 100644
--- a/lib/Target/X86/X86InstrFPStack.td
+++ b/lib/Target/X86/X86InstrFPStack.td
@@ -137,13 +137,12 @@
def FpGETRESULT64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP,
[(set RFP64:$dst, X86fpget)]>; // FPR = ST(0)
-let noResults = 1 in {
- def FpSETRESULT32 : FpI_<(outs), (ins RFP32:$src), SpecialFP,
- [(X86fpset RFP32:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
+def FpSETRESULT32 : FpI_<(outs), (ins RFP32:$src), SpecialFP,
+ [(X86fpset RFP32:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
- def FpSETRESULT64 : FpI_<(outs), (ins RFP64:$src), SpecialFP,
- [(X86fpset RFP64:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
-}
+def FpSETRESULT64 : FpI_<(outs), (ins RFP64:$src), SpecialFP,
+ [(X86fpset RFP64:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
+
// FpI - Floating Point Psuedo Instruction template. Predicated on FPStack.
class FpI<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
FpI_<outs, ins, fp, pattern>, Requires<[FPStack]>;
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 8522d61..e0d284f 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -403,14 +403,14 @@
// Return instructions.
let isTerminator = 1, isReturn = 1, isBarrier = 1,
- hasCtrlDep = 1, noResults = 1 in {
+ hasCtrlDep = 1 in {
def RET : I<0xC3, RawFrm, (outs), (ins), "ret", [(X86retflag 0)]>;
def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), "ret $amt",
[(X86retflag imm:$amt)]>;
}
// All branches are RawFrm, Void, Branch, and Terminators
-let isBranch = 1, isTerminator = 1, noResults = 1 in
+let isBranch = 1, isTerminator = 1 in
class IBr<bits<8> opcode, dag ins, string asm, list<dag> pattern> :
I<opcode, RawFrm, (outs), ins, asm, pattern>;
@@ -418,7 +418,7 @@
let isBranch = 1, isBarrier = 1 in
def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp $dst", [(br bb:$dst)]>;
-let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in {
+let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l} {*}$dst",
[(brind GR32:$dst)]>;
def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l} {*}$dst",
@@ -464,7 +464,7 @@
//===----------------------------------------------------------------------===//
// Call Instructions...
//
-let isCall = 1, noResults = 1 in
+let isCall = 1 in
// All calls clobber the non-callee saved registers...
let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
@@ -478,13 +478,13 @@
}
// Tail call stuff.
-let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp ${dst:call} # TAIL CALL",
[]>;
-let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp {*}$dst # TAIL CALL",
[]>;
-let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
"jmp {*}$dst # TAIL CALL", []>;
@@ -2506,7 +2506,7 @@
// EH Pseudo Instructions
//
let isTerminator = 1, isReturn = 1, isBarrier = 1,
- hasCtrlDep = 1, noResults = 1 in {
+ hasCtrlDep = 1 in {
def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
"ret #eh_return, addr: $addr",
[(X86ehret GR32:$addr)]>;
diff --git a/lib/Target/X86/X86InstrX86-64.td b/lib/Target/X86/X86InstrX86-64.td
index 7479db4..6c216da 100644
--- a/lib/Target/X86/X86InstrX86-64.td
+++ b/lib/Target/X86/X86InstrX86-64.td
@@ -117,7 +117,7 @@
//===----------------------------------------------------------------------===//
// Call Instructions...
//
-let isCall = 1, noResults = 1 in
+let isCall = 1 in
// All calls clobber the non-callee saved registers...
let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
@@ -133,7 +133,7 @@
}
// Branches
-let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in {
+let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q} {*}$dst",
[(brind GR64:$dst)]>;
def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q} {*}$dst",
@@ -597,7 +597,6 @@
// Temporary hack: there is no patterns associated with these instructions
// so we have to tell tblgen that these do not produce results.
-let noResults = 1 in {
def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
"shld{q} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
Imp<[CL],[]>, TB;
@@ -612,7 +611,6 @@
(outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
"shrd{q} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
TB;
-} // noResults
//===----------------------------------------------------------------------===//
// Logical Instructions...