Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via subregisters when 16-bit LEA is disabled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41007 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index d0a0a09..1dbbce2 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -19,6 +19,7 @@
#include "X86TargetMachine.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/LiveVariables.h"
+#include "llvm/CodeGen/SSARegMap.h"
using namespace llvm;
X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
@@ -209,17 +210,53 @@
}
case X86::SHL16ri: {
assert(MI->getNumOperands() == 3 && "Unknown shift instruction!");
- if (DisableLEA16) return 0;
+ // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
+ // the flags produced by a shift yet, so this is safe.
+ unsigned Dest = MI->getOperand(0).getReg();
+ unsigned Src = MI->getOperand(1).getReg();
+ unsigned ShAmt = MI->getOperand(2).getImm();
+ if (ShAmt == 0 || ShAmt >= 4) return 0;
- // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
- // the flags produced by a shift yet, so this is safe.
- unsigned Dest = MI->getOperand(0).getReg();
- unsigned Src = MI->getOperand(1).getReg();
- unsigned ShAmt = MI->getOperand(2).getImm();
- if (ShAmt == 0 || ShAmt >= 4) return 0;
-
- NewMI = BuildMI(get(X86::LEA16r), Dest)
- .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
+ if (DisableLEA16) {
+ // If 16-bit LEA is disabled, use 32-bit LEA via subregisters.
+ SSARegMap *RegMap = MFI->getParent()->getSSARegMap();
+ unsigned Opc, leaInReg, leaOutReg;
+ MVT::ValueType leaVT;
+ if (TM.getSubtarget<X86Subtarget>().is64Bit()) {
+ Opc = X86::LEA64_32r;
+ leaVT = MVT::i64;
+ leaInReg = RegMap->createVirtualRegister(&X86::GR64RegClass);
+ leaOutReg = RegMap->createVirtualRegister(&X86::GR64RegClass);
+ } else {
+ Opc = X86::LEA32r;
+ leaVT = MVT::i32;
+ leaInReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
+ leaOutReg = RegMap->createVirtualRegister(&X86::GR32RegClass);
+ }
+
+ MachineInstr *Ins = NULL, *Ext = NULL;
+
+ Ins = BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2);
+ Ins->copyKillDeadInfo(MI);
+
+ NewMI = BuildMI(get(Opc), leaOutReg)
+ .addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0);
+
+ Ext = BuildMI(get(X86::EXTRACT_SUBREG), Dest).addReg(leaOutReg).addImm(2);
+ Ext->copyKillDeadInfo(MI);
+
+ MFI->insert(MBBI, Ins); // Insert the insert_subreg
+ LV.instructionChanged(MI, NewMI); // Update live variables
+ LV.addVirtualRegisterKilled(leaInReg, NewMI);
+ MFI->insert(MBBI, NewMI); // Insert the new inst
+ LV.addVirtualRegisterKilled(leaOutReg, Ext);
+ MFI->insert(MBBI, Ext); // Insert the extract_subreg
+
+ return Ext;
+ } else {
+ NewMI = BuildMI(get(X86::LEA16r), Dest)
+ .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0);
+ }
break;
}
}