commit 3986924e0b572e90ab0403a4412967da2c5f78d6
author Chris Lattner <sabre@nondot.org> Thu Dec 02 17:57:21 2004 +0000
committer Chris Lattner <sabre@nondot.org> Thu Dec 02 17:57:21 2004 +0000
tree 1403cc0297fcce7d503775dd726f40eb8466b000
parent 0da7f493811653757c0bedc14faaa1ad9e92070c

Consider 64-bit registers to be FP as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18432 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86ISelSimple.cpp

diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp
index 89842a4..b1336f7 100644
--- a/lib/Target/X86/X86ISelSimple.cpp
+++ b/lib/Target/X86/X86ISelSimple.cpp
@@ -815,7 +815,9 @@
       MachineBasicBlock *SBB = *SI;
       for (MachineBasicBlock::iterator I = SBB->begin();
            I != SBB->end() && I->getOpcode() == X86::PHI; ++I) {
-        if (RegMap.getRegClass(I->getOperand(0).getReg())->getSize() == 10)
+        const TargetRegisterClass *RC =
+          RegMap.getRegClass(I->getOperand(0).getReg());
+        if (RC->getSize() == 10 || RC->getSize() == 8)
           goto UsesFPReg;
       }
     }