commit 39b5c0c049a19c7a7feffc9506da07923cc136e4
author Jakob Stoklund Olesen <stoklund@2pi.dk> Thu Nov 29 03:34:17 2012 +0000
committer Jakob Stoklund Olesen <stoklund@2pi.dk> Thu Nov 29 03:34:17 2012 +0000
tree 40e2fe5414f9c051805e7fcd282a671e844e8fbd
parent e26e8a64ab37e98c69801ac2028b187773bc1d1f

Use MCPhysReg for RegisterClassInfo allocation orders.

This saves a bit of memory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168852 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/AggressiveAntiDepBreaker.cpp

diff --git a/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/lib/CodeGen/AggressiveAntiDepBreaker.cpp
index 7a1c049..880a78f 100644
--- a/lib/CodeGen/AggressiveAntiDepBreaker.cpp
+++ b/lib/CodeGen/AggressiveAntiDepBreaker.cpp
@@ -616,7 +616,7 @@
   const TargetRegisterClass *SuperRC =
     TRI->getMinimalPhysRegClass(SuperReg, MVT::Other);
 
-  ArrayRef<unsigned> Order = RegClassInfo.getOrder(SuperRC);
+  ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
   if (Order.empty()) {
     DEBUG(dbgs() << "\tEmpty Super Regclass!!\n");
     return false;