Modify the ISD::ADD opcode case to use new immediate constant predicates.
Includes support for 32-bit constants using addi/addis.
Patch by Jim Laskey.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22711 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index b900c83..6128590 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -1689,19 +1689,23 @@
return Result;
}
Tmp1 = SelectExpr(N.getOperand(0));
- switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
- default: assert(0 && "unhandled result code");
- case 0: // No immediate
- Tmp2 = SelectExpr(N.getOperand(1));
- BuildMI(BB, PPC::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
- break;
- case 1: // Low immediate
+ if (isImmediate(N.getOperand(1), Tmp2)) {
+ Tmp3 = HA16(Tmp2);
+ Tmp2 = Lo16(Tmp2);
+ if (Tmp2 && Tmp3) {
+ unsigned Reg = MakeReg(MVT::i32);
+ BuildMI(BB, PPC::ADDI, 2, Reg).addReg(Tmp1).addSImm(Tmp2);
+ BuildMI(BB, PPC::ADDIS, 2, Result).addReg(Reg).addSImm(Tmp3);
+ } else if (Tmp2) {
BuildMI(BB, PPC::ADDI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
- break;
- case 2: // Shifted immediate
- BuildMI(BB, PPC::ADDIS, 2, Result).addReg(Tmp1).addSImm(Tmp2);
- break;
+ } else {
+ BuildMI(BB, PPC::ADDIS, 2, Result).addReg(Tmp1).addSImm(Tmp3);
+ }
+ return Result;
}
+
+ Tmp2 = SelectExpr(N.getOperand(1));
+ BuildMI(BB, PPC::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
case ISD::AND: