Last round of 2-node folds from SD.cpp. Will move on to 3 node ops such
as setcc and select next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23295 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 055caad..ae0c2c8 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1310,10 +1310,10 @@
}
}
+ if (!CombinerEnabled) {
if (N2C) {
uint64_t C2 = N2C->getValue();
- if (!CombinerEnabled) {
switch (Opcode) {
case ISD::ADD:
if (!C2) return N1; // add X, 0 -> X
@@ -1486,7 +1486,7 @@
if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N1.Val->getOperand(1)))
return getNode(Opcode, VT, N1.Val->getOperand(0),
getNode(Opcode, VT, N2, N1.Val->getOperand(1)));
- }
+ }
}
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1.Val);
@@ -1533,6 +1533,7 @@
case ISD::AND:
case ISD::OR:
+ if (!CombinerEnabled) {
if (N1.Val->getOpcode() == ISD::SETCC && N2.Val->getOpcode() == ISD::SETCC){
SDNode *LHS = N1.Val, *RHS = N2.Val;
SDOperand LL = LHS->getOperand(0), RL = RHS->getOperand(0);
@@ -1595,6 +1596,7 @@
return getNode(ISD::ZERO_EXTEND, VT,
getNode(Opcode, N1.getOperand(0).getValueType(),
N1.getOperand(0), N2.getOperand(0)));
+ }
break;
case ISD::XOR:
if (!CombinerEnabled) {