Fix some code in the current node combining code, spotted when it was moved
over to DAGCombiner.cpp
1. Don't assume that SetCC returns i1 when folding (xor (setcc) constant)
2. Don't duplicate code in folding AND with AssertZext that is handled by
MaskedValueIsZero
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23196 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 3ff1f77..e22d723 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1394,14 +1394,6 @@
// we know the result of the AND will be the AND mask itself.
return N2;
}
- } else if (N1.getOpcode() == ISD::AssertZext) {
- // If we are masking out the part of our input that was already masked
- // out, just return the input directly.
- unsigned ExtendBits =
- MVT::getSizeInBits(cast<VTSDNode>(N1.getOperand(1))->getVT());
- uint64_t ExtendMask = (1ULL << ExtendBits) - 1;
- if (ExtendMask == C2)
- return N1.getOperand(0);
}
break;
case ISD::OR:
@@ -1411,8 +1403,7 @@
break;
case ISD::XOR:
if (!C2) return N1; // X xor 0 -> X
- if (N2C->isAllOnesValue()) {
- if (N1.Val->getOpcode() == ISD::SETCC){
+ if (N2C->getValue() == 1 && N1.Val->getOpcode() == ISD::SETCC) {
SDNode *SetCC = N1.Val;
// !(X op Y) -> (X !op Y)
bool isInteger = MVT::isInteger(SetCC->getOperand(0).getValueType());
@@ -1420,7 +1411,8 @@
return getSetCC(SetCC->getValueType(0),
SetCC->getOperand(0), SetCC->getOperand(1),
ISD::getSetCCInverse(CC, isInteger));
- } else if (N1.getOpcode() == ISD::AND || N1.getOpcode() == ISD::OR) {
+ } else if (N2C->isAllOnesValue()) {
+ if (N1.getOpcode() == ISD::AND || N1.getOpcode() == ISD::OR) {
SDNode *Op = N1.Val;
// !(X or Y) -> (!X and !Y) iff X or Y are freely invertible
// !(X and Y) -> (!X or !Y) iff X or Y are freely invertible