SchedMachineModel: compress the CPU's WriteLatencyTable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164199 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/CodeGenSchedule.h b/utils/TableGen/CodeGenSchedule.h
index dd0bf72..ec556c2 100644
--- a/utils/TableGen/CodeGenSchedule.h
+++ b/utils/TableGen/CodeGenSchedule.h
@@ -284,6 +284,9 @@
unsigned getSchedRWIdx(Record *Def, bool IsRead, unsigned After = 0) const;
+ // Return true if the given write record is referenced by a ReadAdvance.
+ bool hasReadOfWrite(Record *WriteDef) const;
+
// Check if any instructions are assigned to an explicit itinerary class other
// than NoItinerary.
bool hasItineraryClasses() const { return NumItineraryClasses > 0; }