R600: Emit function name in the AsmPrinter
Emitting the function name allows us to check for it in the FileCheck
tests so we can make sure FileCheck is checking the output of the
correct function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174392 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/R600/AMDGPUAsmPrinter.cpp b/lib/Target/R600/AMDGPUAsmPrinter.cpp
index 754506c..715a378 100644
--- a/lib/Target/R600/AMDGPUAsmPrinter.cpp
+++ b/lib/Target/R600/AMDGPUAsmPrinter.cpp
@@ -47,6 +47,9 @@
#endif
}
SetupMachineFunction(MF);
+ if (OutStreamer.hasRawTextSupport()) {
+ OutStreamer.EmitRawText("@" + MF.getName() + ":");
+ }
OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
if (STM.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
EmitProgramInfo(MF);
diff --git a/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll b/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll
index 1acf905..fd958b3 100644
--- a/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll
+++ b/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll
@@ -1,13 +1,15 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
-;CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
; This test is for a bug in
; DAGCombiner::reduceBuildVecConvertToConvertBuildVec() where
; the wrong type was being passed to
; TargetLowering::getOperationAction() when checking the legality of
; ISD::UINT_TO_FP and ISD::SINT_TO_FP opcodes.
+
+; CHECK: @sint
+; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
define void @sint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) {
entry:
%ptr = getelementptr i32 addrspace(1)* %in, i32 1
@@ -19,6 +21,7 @@
ret void
}
+;CHECK: @uint
;CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
define void @uint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) {
diff --git a/test/CodeGen/R600/literals.ll b/test/CodeGen/R600/literals.ll
index 4c731b2..be62342 100644
--- a/test/CodeGen/R600/literals.ll
+++ b/test/CodeGen/R600/literals.ll
@@ -6,6 +6,7 @@
; or
; ADD_INT literal.x REG, 5
+; CHECK; @i32_literal
; CHECK: ADD_INT {{[A-Z0-9,. ]*}}literal.x,{{[A-Z0-9,. ]*}} 5
define void @i32_literal(i32 addrspace(1)* %out, i32 %in) {
entry:
@@ -20,6 +21,7 @@
; or
; ADD literal.x REG, 5.0
+; CHECK: @float_literal
; CHECK: ADD {{[A-Z0-9,. ]*}}literal.x,{{[A-Z0-9,. ]*}} {{[0-9]+}}(5.0
define void @float_literal(float addrspace(1)* %out, float %in) {
entry:
diff --git a/test/CodeGen/R600/short-args.ll b/test/CodeGen/R600/short-args.ll
index 1070250..b69e327 100644
--- a/test/CodeGen/R600/short-args.ll
+++ b/test/CodeGen/R600/short-args.ll
@@ -1,5 +1,6 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; CHECK: @i8_arg
; CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
define void @i8_arg(i32 addrspace(1)* nocapture %out, i8 %in) nounwind {
@@ -9,6 +10,7 @@
ret void
}
+; CHECK: @i8_zext_arg
; CHECK: VTX_READ_8 T{{[0-9]+\.X, T[0-9]+\.X}}
define void @i8_zext_arg(i32 addrspace(1)* nocapture %out, i8 zeroext %in) nounwind {
@@ -18,6 +20,7 @@
ret void
}
+; CHECK: @i16_arg
; CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}
define void @i16_arg(i32 addrspace(1)* nocapture %out, i16 %in) nounwind {
@@ -27,6 +30,7 @@
ret void
}
+; CHECK: @i16_zext_arg
; CHECK: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}
define void @i16_zext_arg(i32 addrspace(1)* nocapture %out, i16 zeroext %in) nounwind {
diff --git a/test/CodeGen/R600/vec4-expand.ll b/test/CodeGen/R600/vec4-expand.ll
index c61f6e2..8f62bc6 100644
--- a/test/CodeGen/R600/vec4-expand.ll
+++ b/test/CodeGen/R600/vec4-expand.ll
@@ -1,5 +1,6 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+; CHECK: @fp_to_sint
; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
@@ -12,6 +13,7 @@
ret void
}
+; CHECK: @fp_to_uint
; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; CHECK: FLT_TO_UINT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
@@ -24,6 +26,7 @@
ret void
}
+; CHECK: @sint_to_fp
; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
@@ -36,6 +39,7 @@
ret void
}
+; CHECK: @uint_to_fp
; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}