Fix some comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22530 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index ee79491..a21cf5b 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -1656,9 +1656,6 @@
return Result;
case ISD::AND:
- // FIXME: should add check in getImmediateForOpcode to return a value
- // indicating the immediate is a run of set bits so we can emit a bitfield
- // clear with RLWINM instead.
switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
default: assert(0 && "unhandled result code");
case 0: // No immediate
@@ -1690,6 +1687,7 @@
Tmp3 = Tmp2 >> 16; // MB
Tmp2 &= 0xFFFF; // ME
+ // FIXME: Catch SHL-AND in addition to SRL-AND in this block.
if (N.getOperand(0).getOpcode() == ISD::SRL)
if (ConstantSDNode *SA =
dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {