diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index ee79491..a21cf5b 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -1656,9 +1656,6 @@
     return Result;
 
   case ISD::AND:
-    // FIXME: should add check in getImmediateForOpcode to return a value
-    // indicating the immediate is a run of set bits so we can emit a bitfield
-    // clear with RLWINM instead.
     switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
       default: assert(0 && "unhandled result code");
       case 0: // No immediate
@@ -1690,6 +1687,7 @@
         Tmp3 = Tmp2 >> 16;  // MB
         Tmp2 &= 0xFFFF;     // ME
 
+        // FIXME: Catch SHL-AND in addition to SRL-AND in this block.
         if (N.getOperand(0).getOpcode() == ISD::SRL)
           if (ConstantSDNode *SA =
               dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 7977a00..3493fdc 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -263,7 +263,7 @@
   // Update frame info to pretend that this is part of the stack...
   MFI->setStackSize(NumBytes);
 
-  // If , adjust stack pointer: r1 -= numbytes.
+  // Adjust stack pointer: r1 -= numbytes.
   if (NumBytes <= 32768) {
     MI=BuildMI(PPC::STWU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
     MBB.insert(MBBI, MI);