Add FP versions of the binary operators, keeping the int and fp worlds seperate.
Though I have done extensive testing, it is possible that this will break
things in configs I can't test. Please let me know if this causes a problem
and I'll fix it ASAP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23505 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 1a20b29..c30c459 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -1275,10 +1275,7 @@
case ISD::SHL: Opc = Alpha::SL; break;
case ISD::SRL: Opc = Alpha::SRL; break;
case ISD::SRA: Opc = Alpha::SRA; break;
- case ISD::MUL:
- Opc = isFP ? (DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS)
- : Alpha::MULQ;
- break;
+ case ISD::MUL: Opc = Alpha::MULQ; break;
};
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));
@@ -1288,25 +1285,7 @@
case ISD::ADD:
case ISD::SUB:
- if (isFP) {
- ConstantFPSDNode *CN;
- if (opcode == ISD::ADD)
- Opc = DestType == MVT::f64 ? Alpha::ADDT : Alpha::ADDS;
- else
- Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS;
- if (opcode == ISD::SUB
- && (CN = dyn_cast<ConstantFPSDNode>(N.getOperand(0)))
- && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)))
- {
- Tmp2 = SelectExpr(N.getOperand(1));
- BuildMI(BB, Alpha::CPYSN, 2, Result).addReg(Tmp2).addReg(Tmp2);
- } else {
- Tmp1 = SelectExpr(N.getOperand(0));
- Tmp2 = SelectExpr(N.getOperand(1));
- BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
- }
- return Result;
- } else {
+ {
bool isAdd = opcode == ISD::ADD;
//first check for Scaled Adds and Subs!
@@ -1369,15 +1348,25 @@
}
return Result;
}
-
+ case ISD::FADD:
+ case ISD::FSUB:
+ case ISD::FMUL:
+ case ISD::FDIV: {
+ if (opcode == ISD::FADD)
+ Opc = DestType == MVT::f64 ? Alpha::ADDT : Alpha::ADDS;
+ else if (opcode == ISD::FSUB)
+ Opc = DestType == MVT::f64 ? Alpha::SUBT : Alpha::SUBS;
+ else if (opcode == ISD::FMUL)
+ Opc = DestType == MVT::f64 ? Alpha::MULT : Alpha::MULS;
+ else
+ Opc = DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS;
+ Tmp1 = SelectExpr(N.getOperand(0));
+ Tmp2 = SelectExpr(N.getOperand(1));
+ BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
+ return Result;
+ }
case ISD::SDIV:
- if (isFP) {
- Tmp1 = SelectExpr(N.getOperand(0));
- Tmp2 = SelectExpr(N.getOperand(1));
- BuildMI(BB, DestType == MVT::f64 ? Alpha::DIVT : Alpha::DIVS, 2, Result)
- .addReg(Tmp1).addReg(Tmp2);
- return Result;
- } else {
+ {
//check if we can convert into a shift!
if (isSIntImmediate(N.getOperand(1), SImm) &&
SImm != 0 && isPowerOf2_64(llabs(SImm))) {