commit 3ee306cbc0a295409c464ffaad5ef694de8eb09a
author Akira Hatanaka <ahatanaka@mips.com> Mon Jul 23 23:45:54 2012 +0000
committer Akira Hatanaka <ahatanaka@mips.com> Mon Jul 23 23:45:54 2012 +0000
tree 0f0cb3e4eac9c89a2931eeb2bfc7e6c8a5615e1a
parent 581a739226381450ea2271cc794618043b6aeb4a

Add basic ability to setup call frame, and make procedure calls.
Hello world will compile and execute with this patch.

Patch by Reed Kotler.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160651 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/MipsISelDAGToDAG.cpp

diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp
index c409e57..ea33b74 100644
--- a/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -128,18 +128,21 @@
   const MipsInstrInfo *MII = TM.getInstrInfo();
   const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
   DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
-  unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
-  int FI = 0; 
+  unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
+  int FI = 0;
 
-  if (!Subtarget.inMips16Mode())
-    FI= MipsFI->initGlobalRegFI();
+  FI= MipsFI->initGlobalRegFI();
 
   const TargetRegisterClass *RC = Subtarget.isABI_N64() ?
     (const TargetRegisterClass*)&Mips::CPU64RegsRegClass :
     (const TargetRegisterClass*)&Mips::CPURegsRegClass;
 
+  if (Subtarget.inMips16Mode())
+    RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
+
   V0 = RegInfo.createVirtualRegister(RC);
   V1 = RegInfo.createVirtualRegister(RC);
+  V2 = RegInfo.createVirtualRegister(RC);
 
   if (Subtarget.isABI_N64()) {
     MF.getRegInfo().addLiveIn(Mips::T9_64);
@@ -160,6 +163,21 @@
     return;
   }
 
+  if (Subtarget.inMips16Mode()) {
+    BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
+        .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
+    BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16),
+            V1)
+        .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
+    BuildMI(MBB, I, DL, TII.get(Mips::SllX16),
+            V2 ).addReg(V0).addImm(16);
+    BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
+      .addReg(V1).addReg(V2);
+
+
+    return;
+  }
+
   if (MF.getTarget().getRelocationModel() == Reloc::Static) {
     // Set global register to __gnu_local_gp.
     //
@@ -169,8 +187,6 @@
       .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
     BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
       .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
-    MII->storeRegToStackSlot(MBB, I, GlobalBaseReg, false, FI, RC,
-                             TargetRegInfo);
     return;
   }
 
@@ -194,8 +210,10 @@
 
   assert(Subtarget.isABI_O32());
 
-  if (Subtarget.inMips16Mode())
-    return; // no need to load GP. It can be calculated anywhere
+
+  //if (Subtarget.inMips16Mode())
+  //  return; // no need to load GP. It can be calculated anywhere
+
 
 
   // For O32 ABI, the following instruction sequence is emitted to initialize