R600: Add support for 24-bit MUL instructions
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186922 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
index e4fb07d..6969109 100644
--- a/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
+++ b/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
@@ -58,6 +58,9 @@
bool SelectADDRParam(SDValue Addr, SDValue& R1, SDValue& R2);
bool SelectADDR(SDValue N, SDValue &R1, SDValue &R2);
bool SelectADDR64(SDValue N, SDValue &R1, SDValue &R2);
+ SDValue SimplifyI24(SDValue &Op);
+ bool SelectI24(SDValue Addr, SDValue &Op);
+ bool SelectU24(SDValue Addr, SDValue &Op);
static bool checkType(const Value *ptr, unsigned int addrspace);
@@ -674,7 +677,9 @@
#endif
#undef DEBUGTMP
-///==== AMDGPU Functions ====///
+//===----------------------------------------------------------------------===//
+// Complex Patterns
+//===----------------------------------------------------------------------===//
bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
SDValue& IntPtr) {
@@ -741,6 +746,49 @@
return true;
}
+SDValue AMDGPUDAGToDAGISel::SimplifyI24(SDValue &Op) {
+ APInt Demanded = APInt(32, 0x00FFFFFF);
+ APInt KnownZero, KnownOne;
+ TargetLowering::TargetLoweringOpt TLO(*CurDAG, true, true);
+ const TargetLowering *TLI = getTargetLowering();
+ if (TLI->SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) {
+ CurDAG->ReplaceAllUsesWith(Op, TLO.New);
+ CurDAG->RepositionNode(Op.getNode(), TLO.New.getNode());
+ return SimplifyI24(TLO.New);
+ } else {
+ return Op;
+ }
+}
+
+bool AMDGPUDAGToDAGISel::SelectI24(SDValue Op, SDValue &I24) {
+
+ assert(Op.getValueType() == MVT::i32);
+
+ if (CurDAG->ComputeNumSignBits(Op) == 9) {
+ I24 = SimplifyI24(Op);
+ return true;
+ }
+ return false;
+}
+
+bool AMDGPUDAGToDAGISel::SelectU24(SDValue Op, SDValue &U24) {
+ APInt KnownZero;
+ APInt KnownOne;
+ CurDAG->ComputeMaskedBits(Op, KnownZero, KnownOne);
+
+ assert (Op.getValueType() == MVT::i32);
+
+ // ANY_EXTEND and EXTLOAD operations can only be done on types smaller than
+ // i32. These smaller types are legal to use with the i24 instructions.
+ if ((KnownZero & APInt(KnownZero.getBitWidth(), 0xFF000000)) == 0xFF000000 ||
+ Op.getOpcode() == ISD::ANY_EXTEND ||
+ ISD::isEXTLoad(Op.getNode())) {
+ U24 = SimplifyI24(Op);
+ return true;
+ }
+ return false;
+}
+
void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
if (Subtarget.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
diff --git a/lib/Target/R600/AMDGPUInstructions.td b/lib/Target/R600/AMDGPUInstructions.td
index 04618f2..d6a7759 100644
--- a/lib/Target/R600/AMDGPUInstructions.td
+++ b/lib/Target/R600/AMDGPUInstructions.td
@@ -173,6 +173,9 @@
[{return N->isExactlyValue(1.0);}]
>;
+def U24 : ComplexPattern<i32, 1, "SelectU24", [], []>;
+def I24 : ComplexPattern<i32, 1, "SelectI24", [], []>;
+
let isCodeGenOnly = 1, isPseudo = 1 in {
let usesCustomInserter = 1 in {
@@ -366,6 +369,16 @@
(BIT_ALIGN $src0, $src0, $src1)
>;
+// 24-bit arithmetic patterns
+def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
+
+/*
+class UMUL24Pattern <Instruction UMUL24> : Pat <
+ (mul U24:$x, U24:$y),
+ (UMUL24 $x, $y)
+>;
+*/
+
include "R600Instructions.td"
include "SIInstrInfo.td"
diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td
index 9aeebc9..56015ea 100644
--- a/lib/Target/R600/R600Instructions.td
+++ b/lib/Target/R600/R600Instructions.td
@@ -1473,6 +1473,9 @@
def CNDGE_eg : CNDGE_Common<0x1B>;
def MUL_LIT_eg : MUL_LIT_Common<0x1F>;
def LOG_CLAMPED_eg : LOG_CLAMPED_Common<0x82>;
+ def MUL_UINT24_eg : R600_2OP <0xB5, "MUL_UINT24",
+ [(set i32:$dst, (mul U24:$src0, U24:$src1))], VecALU
+ >;
def DOT4_eg : DOT4_Common<0xBE>;
defm CUBE_eg : CUBE_Common<0xC0>;
@@ -1703,6 +1706,10 @@
let Predicates = [isCayman] in {
+def MUL_INT24_cm : R600_2OP <0x5B, "MUL_INT24",
+ [(set i32:$dst, (mul I24:$src0, I24:$src1))], VecALU
+>;
+
let isVector = 1 in {
def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>;
diff --git a/lib/Target/R600/SIInstructions.td b/lib/Target/R600/SIInstructions.td
index 61163c2..8f3baaa 100644
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -866,14 +866,16 @@
[(set f32:$dst, (fmul f32:$src0, f32:$src1))]
>;
-} // End isCommutable = 1
-//defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24", []>;
+defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24",
+ [(set i32:$dst, (mul I24:$src0, I24:$src1))]
+>;
//defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>;
-//defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24", []>;
+defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24",
+ [(set i32:$dst, (mul U24:$src0, U24:$src1))]
+>;
//defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>;
-let isCommutable = 1 in {
defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32",
[(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))]