enable PPC register scavenging by default (update tests and remove some FIXMEs)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145819 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll b/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll
index e50fac4..d10291e 100644
--- a/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll
+++ b/test/CodeGen/PowerPC/2008-03-05-RegScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=powerpc-apple-darwin -enable-ppc32-regscavenger
+; RUN: llc < %s -mtriple=powerpc-apple-darwin
declare i8* @bar(i32)
diff --git a/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll b/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll
index 9f35b83..fb8cdce 100644
--- a/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll
+++ b/test/CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=ppc32 -enable-ppc32-regscavenger
+; RUN: llc < %s -march=ppc32
%struct._cpp_strbuf = type { i8*, i32, i32 }
%struct.cpp_string = type { i32, i8* }
diff --git a/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll b/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll
index dd425f5..f256bca 100644
--- a/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll
+++ b/test/CodeGen/PowerPC/2008-03-18-RegScavengerAssert.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=ppc64 -enable-ppc64-regscavenger
+; RUN: llc < %s -march=ppc64
define i16 @test(i8* %d1, i16* %d2) {
%tmp237 = call i16 asm "lhbrx $0, $2, $1", "=r,r,bO,m"( i8* %d1, i32 0, i16* %d2 )
diff --git a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
index b2ed74f..3315750 100644
--- a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
+++ b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll
@@ -6,11 +6,11 @@
define void @foo() nounwind {
entry:
-;CHECK: mfcr r2
-;CHECK: lis r0, 1
-;CHECK: rlwinm r2, r2, 8, 0, 31
-;CHECK: ori r0, r0, 34524
-;CHECK: stwx r2, r1, r0
+;CHECK: lis r4, 1
+;CHECK: ori r4, r4, 34524
+;CHECK: mfcr r3
+;CHECK: rlwinm r3, r3, 8, 0, 31
+;CHECK: stwx r3, r1, r4
%x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1]
%"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0]
%x1 = bitcast [100000 x i8]* %x to i8* ; <i8*> [#uses=1]
@@ -19,9 +19,9 @@
br label %return
return: ; preds = %entry
-;CHECK: lis r0, 1
-;CHECK: ori r0, r0, 34524
-;CHECK: lwzx r2, r1, r0
+;CHECK: lis r3, 1
+;CHECK: ori r3, r3, 34524
+;CHECK: lwzx r2, r1, r3
;CHECK: rlwinm r2, r2, 24, 0, 31
;CHECK: mtcrf 32, r2
ret void
diff --git a/test/CodeGen/PowerPC/Frames-alloca.ll b/test/CodeGen/PowerPC/Frames-alloca.ll
index 466ae80..28dd08c 100644
--- a/test/CodeGen/PowerPC/Frames-alloca.ll
+++ b/test/CodeGen/PowerPC/Frames-alloca.ll
@@ -2,9 +2,9 @@
; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC64
; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-NOFP
; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC64-NOFP
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS-NOFP
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC32
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 | FileCheck %s -check-prefix=PPC32-RS
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-RS-NOFP
; CHECK-PPC32: stw r31, -4(r1)
; CHECK-PPC32: lwz r1, 0(r1)
diff --git a/test/CodeGen/PowerPC/ppc32-vaarg.ll b/test/CodeGen/PowerPC/ppc32-vaarg.ll
index 725c106..c2680fb 100644
--- a/test/CodeGen/PowerPC/ppc32-vaarg.ll
+++ b/test/CodeGen/PowerPC/ppc32-vaarg.ll
@@ -37,8 +37,8 @@
; CHECK-NEXT: stw 3, -24(1)
; CHECK-NEXT: stw 8, -28(1)
; CHECK-NEXT: stw 6, -32(1)
-; CHECK-NEXT: mfcr 0 # cr0
-; CHECK-NEXT: stw 0, -36(1)
+; CHECK-NEXT: mfcr 3 # cr0
+; CHECK-NEXT: stw 3, -36(1)
; CHECK-NEXT: blt 0, .LBB0_4
; CHECK-NEXT: # BB#3: # %entry
; CHECK-NEXT: lwz 3, -20(1)
@@ -82,8 +82,8 @@
; CHECK-NEXT: stw 4, -52(1)
; CHECK-NEXT: stw 6, -56(1)
; CHECK-NEXT: stw 8, -60(1)
-; CHECK-NEXT: mfcr 0 # cr0
-; CHECK-NEXT: stw 0, -64(1)
+; CHECK-NEXT: mfcr 3 # cr0
+; CHECK-NEXT: stw 3, -64(1)
; CHECK-NEXT: blt 0, .LBB0_8
; CHECK-NEXT: # BB#7: # %entry
; CHECK-NEXT: lwz 3, -48(1)
@@ -122,8 +122,8 @@
; CHECK-NEXT: mr 8, 5
; CHECK-NEXT: stw 4, -72(1)
; CHECK-NEXT: stw 6, -76(1)
-; CHECK-NEXT: mfcr 0 # cr0
-; CHECK-NEXT: stw 0, -80(1)
+; CHECK-NEXT: mfcr 3 # cr0
+; CHECK-NEXT: stw 3, -80(1)
; CHECK-NEXT: stw 5, -84(1)
; CHECK-NEXT: stw 8, -88(1)
; CHECK-NEXT: stw 7, -92(1)