Allow insert_subreg into implicit, target-specific values.
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48130 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 6036dcb..ac7957c 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1491,22 +1491,27 @@
AddToISelQueue(N0);
if (NVT == MVT::i64 || NVT == MVT::i32 || NVT == MVT::i16) {
SDOperand SRIdx;
+ SDOperand ImplVal = CurDAG->getTargetConstant(X86::IMPL_VAL_UNDEF,
+ MVT::i32);
switch(N0.getValueType()) {
case MVT::i32:
- SRIdx = CurDAG->getTargetConstant(3, MVT::i32); // SubRegSet 3
+ SRIdx = CurDAG->getTargetConstant(X86::SUBREG_32BIT, MVT::i32);
+ // x86-64 zero extends 32-bit inserts int 64-bit registers
+ if (Subtarget->is64Bit())
+ ImplVal = CurDAG->getTargetConstant(X86::IMPL_VAL_ZERO, MVT::i32);
break;
case MVT::i16:
- SRIdx = CurDAG->getTargetConstant(2, MVT::i32); // SubRegSet 2
+ SRIdx = CurDAG->getTargetConstant(X86::SUBREG_16BIT, MVT::i32);
break;
case MVT::i8:
if (Subtarget->is64Bit())
- SRIdx = CurDAG->getTargetConstant(1, MVT::i32); // SubRegSet 1
+ SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, MVT::i32);
break;
default: assert(0 && "Unknown any_extend!");
}
if (SRIdx.Val) {
SDNode *ResNode = CurDAG->getTargetNode(X86::INSERT_SUBREG,
- NVT, N0, SRIdx);
+ NVT, ImplVal, N0, SRIdx);
#ifndef NDEBUG
DOUT << std::string(Indent-2, ' ') << "=> ";