commit 4072886a690a853c57c79a87a6423a7bfe0ce61f
author Daniel Dunbar <daniel@zuster.org> Thu May 20 20:20:32 2010 +0000
committer Daniel Dunbar <daniel@zuster.org> Thu May 20 20:20:32 2010 +0000
tree c984ece9fc7295769df2fa262ef47ec77c31feb3
parent c6519f916b5922de81c53547fd21364994195a70

tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor
it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104270 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/X86RecognizableInstr.cpp

diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp
index 94ed15b..b7085ae 100644
--- a/utils/TableGen/X86RecognizableInstr.cpp
+++ b/utils/TableGen/X86RecognizableInstr.cpp
@@ -230,6 +230,10 @@
                                    const CodeGenInstruction &insn,
                                    InstrUID uid)
 {
+  // Ignore "asm parser only" instructions.
+  if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
+    return;
+  
   RecognizableInstr recogInstr(tables, insn, uid);
   
   recogInstr.emitInstructionSpecifier(tables);