DebugLoc form of getNOT().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63433 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 16f17e5..d573476 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -846,6 +846,23 @@
return getNode(ISD::XOR, VT, Val, NegOne);
}
+/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
+///
+SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) {
+ SDValue NegOne;
+ if (VT.isVector()) {
+ MVT EltVT = VT.getVectorElementType();
+ SDValue NegOneElt = getConstant(EltVT.getIntegerVTBitMask(), EltVT);
+ std::vector<SDValue> NegOnes(VT.getVectorNumElements(), NegOneElt);
+ NegOne = getNode(ISD::BUILD_VECTOR, DebugLoc::getUnknownLoc(), VT,
+ &NegOnes[0], NegOnes.size());
+ } else {
+ NegOne = getConstant(VT.getIntegerVTBitMask(), VT);
+ }
+
+ return getNode(ISD::XOR, DL, VT, Val, NegOne);
+}
+
SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) {
MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
assert((EltVT.getSizeInBits() >= 64 ||