Updates to match change of getRegForInlineAsmConstraint prototype
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26305 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 533499c..79211de 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -745,7 +745,8 @@
std::vector<unsigned> TargetLowering::
-getRegForInlineAsmConstraint(const std::string &Constraint) const {
+getRegForInlineAsmConstraint(const std::string &Constraint,
+ MVT::ValueType VT) const {
// Not a physreg, must not be a register reference or something.
if (Constraint[0] != '{') return std::vector<unsigned>();
assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");