Add implicit def / use operands to MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31633 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 472a8d7..730ad23 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -658,16 +658,9 @@
}
for (; MI != miEnd; ++MI) {
- const TargetInstrDescriptor &TID = tii_->get(MI->getOpcode());
DEBUG(std::cerr << MIIndex << "\t" << *MI);
-
- // Handle implicit defs.
- if (TID.ImplicitDefs) {
- for (const unsigned *ImpDef = TID.ImplicitDefs; *ImpDef; ++ImpDef)
- handleRegisterDef(MBB, MI, MIIndex, *ImpDef);
- }
- // Handle explicit defs.
+ // Handle defs.
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
MachineOperand &MO = MI->getOperand(i);
// handle register defs - build intervals
diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index 2968655..3424f45 100644
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -228,7 +228,6 @@
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
I != E; ++I) {
MachineInstr *MI = I;
- const TargetInstrDescriptor &MID = TII.get(MI->getOpcode());
// Process all of the operands of the instruction...
unsigned NumOperandsToProcess = MI->getNumOperands();
@@ -238,14 +237,7 @@
if (MI->getOpcode() == TargetInstrInfo::PHI)
NumOperandsToProcess = 1;
- // Loop over implicit uses, using them.
- if (MID.ImplicitUses) {
- for (const unsigned *ImplicitUses = MID.ImplicitUses;
- *ImplicitUses; ++ImplicitUses)
- HandlePhysRegUse(*ImplicitUses, MI);
- }
-
- // Process all explicit uses...
+ // Process all uses...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.isUse() && MO.getReg()) {
@@ -258,14 +250,7 @@
}
}
- // Loop over implicit defs, defining them.
- if (MID.ImplicitDefs) {
- for (const unsigned *ImplicitDefs = MID.ImplicitDefs;
- *ImplicitDefs; ++ImplicitDefs)
- HandlePhysRegDef(*ImplicitDefs, MI);
- }
-
- // Process all explicit defs...
+ // Process all defs...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.isDef() && MO.getReg()) {
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index a47293e..ba75e73 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -205,8 +205,12 @@
OS << " ";
::print(mop, OS, TM);
- if (mop.isReg() && mop.isDef())
- OS << "<def>";
+ if (mop.isReg()) {
+ if (mop.isImplicit())
+ OS << (mop.isDef() ? "<imp-def>" : "<imp-use>");
+ else if (mop.isDef())
+ OS << "<def>";
+ }
}
OS << "\n";
diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index e42603e..f911666 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -561,7 +561,7 @@
for (unsigned i = 0; i != MI->getNumOperands(); ++i) {
MachineOperand& MO = MI->getOperand(i);
// here we are looking for only used operands (never def&use)
- if (MO.isRegister() && !MO.isDef() && MO.getReg() &&
+ if (MO.isRegister() && !MO.isDef() && !MO.isImplicit() && MO.getReg() &&
MRegisterInfo::isVirtualRegister(MO.getReg()))
MI = reloadVirtReg(MBB, MI, i);
}
@@ -596,7 +596,7 @@
// are defined, and marking explicit destinations in the PhysRegsUsed map.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
MachineOperand& MO = MI->getOperand(i);
- if (MO.isRegister() && MO.isDef() && MO.getReg() &&
+ if (MO.isRegister() && MO.isDef() && !MO.isImplicit() && MO.getReg() &&
MRegisterInfo::isPhysicalRegister(MO.getReg())) {
unsigned Reg = MO.getReg();
if (PhysRegsUsed[Reg] == -2) continue; // Something like ESP.
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index dd968ed..307b2b9 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -441,6 +441,18 @@
}
}
+ // Emit implicit def / use operands.
+ if (II.ImplicitDefs) {
+ for (const unsigned *ImplicitDefs = II.ImplicitDefs;
+ *ImplicitDefs; ++ImplicitDefs)
+ MI->addRegOperand(*ImplicitDefs, true, true);
+ }
+ if (II.ImplicitUses) {
+ for (const unsigned *ImplicitUses = II.ImplicitUses;
+ *ImplicitUses; ++ImplicitUses)
+ MI->addRegOperand(*ImplicitUses, false, true);
+ }
+
// Now that we have emitted all operands, emit this instruction itself.
if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
BB->insert(BB->end(), MI);