diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp
index 1d9effb..e832978 100644
--- a/lib/CodeGen/RegisterScavenging.cpp
+++ b/lib/CodeGen/RegisterScavenging.cpp
@@ -37,11 +37,12 @@
     const MachineOperand &MO = MI->getOperand(i);
     if (!MO.isRegister())
       continue;
-    if (TRI->isSuperRegister(SubReg, MO.getReg()))
+    if (TRI->isSuperRegister(SubReg, MO.getReg())) {
       if (MO.isUse())
         SeenSuperUse = true;
       else if (MO.isImplicit())
         SeenSuperDef = true;
+    }
   }
 
   return SeenSuperDef && SeenSuperUse;
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index ff505f2..44c72b6 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2986,7 +2986,7 @@
   }
 
   bool Indexed = AM != ISD::UNINDEXED;
-  assert(Indexed || Offset.getOpcode() == ISD::UNDEF &&
+  assert((Indexed || Offset.getOpcode() == ISD::UNDEF) &&
          "Unindexed load with an offset!");
 
   SDVTList VTs = Indexed ?