Add support for 64-bit logical NOR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141029 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td
index 3f52e9e..cd185f6 100644
--- a/lib/Target/Mips/Mips64InstrInfo.td
+++ b/lib/Target/Mips/Mips64InstrInfo.td
@@ -72,6 +72,12 @@
!strconcat(instr_asm, "\t$dst, $b, $c"),
[(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, immZExt16:$c))], IIAlu>;
+let isCommutable = 1 in
+class LogicNOR64<bits<6> op, bits<6> func, string instr_asm>:
+ FR<op, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, CPU64Regs:$c),
+ !strconcat(instr_asm, "\t$dst, $b, $c"),
+ [(set CPU64Regs:$dst, (not (or CPU64Regs:$b, CPU64Regs:$c)))], IIAlu>;
+
// Shifts
class LogicR_shift_rotate_imm64<bits<6> func, bits<5> _rs, string instr_asm,
SDNode OpNode, PatFrag PF>:
@@ -141,6 +147,7 @@
def DAND : LogicR64<0x24, "and", and>;
def DOR : LogicR64<0x25, "or", or>;
def DXOR : LogicR64<0x26, "xor", xor>;
+def DNOR : LogicNOR64<0x00, 0x27, "nor">;
/// Shift Instructions
def DSLL : LogicR_shift_rotate_imm64<0x38, 0x00, "dsll", shl, immZExt5>;
diff --git a/test/CodeGen/Mips/mips64instrs.ll b/test/CodeGen/Mips/mips64instrs.ll
index 16bca0f..8c02a2d 100644
--- a/test/CodeGen/Mips/mips64instrs.ll
+++ b/test/CodeGen/Mips/mips64instrs.ll
@@ -133,3 +133,11 @@
ret i64 %tmp1
}
+define i64 @f20(i64 %a, i64 %b) nounwind readnone {
+entry:
+; CHECK: nor
+ %or = or i64 %b, %a
+ %neg = xor i64 %or, -1
+ ret i64 %neg
+}
+