another solution to the fsel issue. Instead of having 4 variants, just force
the comparison to be 64-bits. This is fine because extensions from float
to double are free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23589 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 729ffb5..5bae7c9 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -815,12 +815,15 @@
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));
Tmp3 = SelectExpr(N.getOperand(2));
- if (N.getOperand(0).getValueType() == MVT::f32)
- Opc = N.getOperand(0).getValueType() == MVT::f32 ?
- PPC::FSELSS : PPC::FSELSD;
- else
- Opc = N.getOperand(0).getValueType() == MVT::f64 ?
- PPC::FSELDD : PPC::FSELDS;
+
+ // Extend the comparison to 64-bits if needed.
+ if (N.getOperand(0).getValueType() == MVT::f32) {
+ unsigned Tmp1New = MakeReg(MVT::f64);
+ BuildMI(BB, PPC::FMRSD, 1, Tmp1New).addReg(Tmp1);
+ Tmp1 = Tmp1New;
+ }
+
+ Opc = N.Val->getValueType(0) == MVT::f32 ? PPC::FSELS : PPC::FSELD;
BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
return Result;
case PPCISD::FCFID: