This target doesn't support fabs/fneg yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21010 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index ba5178b..7242f8f 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -75,6 +75,10 @@
setOperationAction(ISD::MEMSET , MVT::Other, Expand);
setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
+ // We don't support these yet.
+ setOperationAction(ISD::FNEG , MVT::f64 , Expand);
+ setOperationAction(ISD::FABS , MVT::f64 , Expand);
+
//Doesn't work yet
setOperationAction(ISD::SETCC , MVT::f32, Promote);
diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index 16607cb..bb31fc7 100644
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -80,6 +80,9 @@
setOperationAction(ISD::MEMSET , MVT::Other, Expand);
setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
+ // We don't support these yet.
+ setOperationAction(ISD::FNEG , MVT::f64 , Expand);
+ setOperationAction(ISD::FABS , MVT::f64 , Expand);
computeRegisterProperties();
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index a6ebbad..751b553 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -53,6 +53,10 @@
// PowerPC has an i16 but no i8 (or i1) SEXTLOAD
setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
+
+ // We don't support these yet.
+ setOperationAction(ISD::FNEG , MVT::f64 , Expand);
+ setOperationAction(ISD::FABS , MVT::f64 , Expand);
addLegalFPImmediate(+0.0); // Necessary for FSEL
addLegalFPImmediate(-0.0); //
diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index ff23e66..c81b779 100644
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -63,6 +63,10 @@
setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
setOperationAction(ISD::SREM , MVT::f64 , Expand);
+
+ // We don't support these yet.
+ setOperationAction(ISD::FNEG , MVT::f64 , Expand);
+ setOperationAction(ISD::FABS , MVT::f64 , Expand);
// These should be promoted to a larger select which is supported.
/**/ setOperationAction(ISD::SELECT , MVT::i1 , Promote);