Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminating
the need for a flavor operand, and add a new SDNode subclass,
LabelSDNode, for use with them to eliminate the need for a label id
operand.
Change instruction selection to let these label nodes through
unmodified instead of creating copies of them. Teach the MachineInstr
emitter how to emit a MachineInstr directly from an ISD label node.
This avoids the need for allocating SDNodes for the label id and
flavor value, as well as SDNodes for each of the post-isel label,
label id, and label flavor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/BranchFolding.cpp b/lib/CodeGen/BranchFolding.cpp
index f629ae7..6825bfb 100644
--- a/lib/CodeGen/BranchFolding.cpp
+++ b/lib/CodeGen/BranchFolding.cpp
@@ -114,12 +114,12 @@
while (!MBB->succ_empty())
MBB->removeSuccessor(MBB->succ_end()-1);
- // If there is DWARF info to active, check to see if there are any LABEL
+ // If there is DWARF info to active, check to see if there are any DBG_LABEL
// records in the basic block. If so, unregister them from MachineModuleInfo.
if (MMI && !MBB->empty()) {
for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
I != E; ++I) {
- if ((unsigned)I->getOpcode() == TargetInstrInfo::LABEL) {
+ if ((unsigned)I->getOpcode() == TargetInstrInfo::DBG_LABEL) {
// The label ID # is always operand #0, an immediate.
MMI->InvalidateLabel(I->getOperand(0).getImm());
}
diff --git a/lib/CodeGen/Collector.cpp b/lib/CodeGen/Collector.cpp
index 6c5263d..bbb3b93 100644
--- a/lib/CodeGen/Collector.cpp
+++ b/lib/CodeGen/Collector.cpp
@@ -337,7 +337,7 @@
unsigned MachineCodeAnalysis::InsertLabel(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const {
unsigned Label = MMI->NextLabelID();
- BuildMI(MBB, MI, TII->get(TargetInstrInfo::LABEL)).addImm(Label).addImm(2);
+ BuildMI(MBB, MI, TII->get(TargetInstrInfo::GC_LABEL)).addImm(Label);
return Label;
}
diff --git a/lib/CodeGen/DwarfWriter.cpp b/lib/CodeGen/DwarfWriter.cpp
index f068744..a337739 100644
--- a/lib/CodeGen/DwarfWriter.cpp
+++ b/lib/CodeGen/DwarfWriter.cpp
@@ -3260,7 +3260,7 @@
I != E; ++I) {
for (MachineBasicBlock::const_iterator MI = I->begin(), E = I->end();
MI != E; ++MI) {
- if (MI->getOpcode() != TargetInstrInfo::LABEL) {
+ if (!MI->isLabel()) {
SawPotentiallyThrowing |= MI->getDesc().isCall();
continue;
}
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 18810f2..75b2c98 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -523,10 +523,18 @@
}
+/// isLabel - Returns true if the MachineInstr represents a label.
+///
+bool MachineInstr::isLabel() const {
+ return getOpcode() == TargetInstrInfo::DBG_LABEL ||
+ getOpcode() == TargetInstrInfo::EH_LABEL ||
+ getOpcode() == TargetInstrInfo::GC_LABEL;
+}
+
/// isDebugLabel - Returns true if the MachineInstr represents a debug label.
///
bool MachineInstr::isDebugLabel() const {
- return getOpcode() == TargetInstrInfo::LABEL && getOperand(1).getImm() == 0;
+ return getOpcode() == TargetInstrInfo::DBG_LABEL;
}
/// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 3665ee0..4548894 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -1084,28 +1084,26 @@
case TargetLowering::Expand: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
- bool useLABEL = TLI.isOperationLegal(ISD::LABEL, MVT::Other);
+ bool useLABEL = TLI.isOperationLegal(ISD::DBG_LABEL, MVT::Other);
const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
if (MMI && (useDEBUG_LOC || useLABEL)) {
const CompileUnitDesc *CompileUnit = DSP->getCompileUnit();
unsigned SrcFile = MMI->RecordSource(CompileUnit);
- SmallVector<SDOperand, 8> Ops;
- Ops.push_back(Tmp1); // chain
unsigned Line = DSP->getLine();
unsigned Col = DSP->getColumn();
if (useDEBUG_LOC) {
+ SmallVector<SDOperand, 8> Ops;
+ Ops.push_back(Tmp1); // chain
Ops.push_back(DAG.getConstant(Line, MVT::i32)); // line #
Ops.push_back(DAG.getConstant(Col, MVT::i32)); // col #
Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, &Ops[0], Ops.size());
} else {
unsigned ID = MMI->RecordSourceLine(Line, Col, SrcFile);
- Ops.push_back(DAG.getConstant(ID, MVT::i32));
- Ops.push_back(DAG.getConstant(0, MVT::i32)); // a debug label
- Result = DAG.getNode(ISD::LABEL, MVT::Other, &Ops[0], Ops.size());
+ Result = DAG.getLabel(ISD::DBG_LABEL, Tmp1, ID);
}
} else {
Result = Tmp1; // chain
@@ -1163,15 +1161,14 @@
}
break;
- case ISD::LABEL:
- assert(Node->getNumOperands() == 3 && "Invalid LABEL node!");
- switch (TLI.getOperationAction(ISD::LABEL, MVT::Other)) {
+ case ISD::DBG_LABEL:
+ case ISD::EH_LABEL:
+ assert(Node->getNumOperands() == 1 && "Invalid LABEL node!");
+ switch (TLI.getOperationAction(Node->getOpcode(), MVT::Other)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Legal:
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
- Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
- Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the "flavor" operand.
- Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
+ Result = DAG.UpdateNodeOperands(Result, Tmp1);
break;
case TargetLowering::Expand:
Result = LegalizeOp(Node->getOperand(0));
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 7194ed0..de2c1bc 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -879,10 +879,17 @@
assert(0 && "EntryToken should have been excluded from the schedule!");
break;
case ISD::TokenFactor: // fall thru
- case ISD::LABEL:
case ISD::DECLARE:
case ISD::SRCVALUE:
break;
+ case ISD::DBG_LABEL:
+ BB->push_back(BuildMI(TII->get(TargetInstrInfo::DBG_LABEL))
+ .addImm(cast<LabelSDNode>(Node)->getLabelID()));
+ break;
+ case ISD::EH_LABEL:
+ BB->push_back(BuildMI(TII->get(TargetInstrInfo::EH_LABEL))
+ .addImm(cast<LabelSDNode>(Node)->getLabelID()));
+ break;
case ISD::CopyToReg: {
unsigned SrcReg;
SDOperand SrcVal = Node->getOperand(2);
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index c364e1f..17a5fa7 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -192,19 +192,15 @@
/// isDebugLabel - Return true if the specified node represents a debug
-/// label (i.e. ISD::LABEL or TargetInstrInfo::LABEL node and third operand
-/// is 0).
+/// label (i.e. ISD::DBG_LABEL or TargetInstrInfo::DBG_LABEL node).
bool ISD::isDebugLabel(const SDNode *N) {
SDOperand Zero;
- if (N->getOpcode() == ISD::LABEL)
- Zero = N->getOperand(2);
- else if (N->isTargetOpcode() &&
- N->getTargetOpcode() == TargetInstrInfo::LABEL)
- // Chain moved to last operand.
- Zero = N->getOperand(1);
- else
- return false;
- return isa<ConstantSDNode>(Zero) && cast<ConstantSDNode>(Zero)->isNullValue();
+ if (N->getOpcode() == ISD::DBG_LABEL)
+ return true;
+ if (N->isTargetOpcode() &&
+ N->getTargetOpcode() == TargetInstrInfo::DBG_LABEL)
+ return true;
+ return false;
}
/// getSetCCSwappedOperands - Return the operation corresponding to (Y op X)
@@ -389,6 +385,10 @@
ID.AddPointer(DSP->getCompileUnit());
break;
}
+ case ISD::DBG_LABEL:
+ case ISD::EH_LABEL:
+ ID.AddInteger(cast<LabelSDNode>(N)->getLabelID());
+ break;
case ISD::SRCVALUE:
ID.AddPointer(cast<SrcValueSDNode>(N)->getValue());
break;
@@ -1018,6 +1018,22 @@
return SDOperand(N, 0);
}
+SDOperand SelectionDAG::getLabel(unsigned Opcode,
+ SDOperand Root,
+ unsigned LabelID) {
+ FoldingSetNodeID ID;
+ SDOperand Ops[] = { Root };
+ AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1);
+ ID.AddInteger(LabelID);
+ void *IP = 0;
+ if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
+ return SDOperand(E, 0);
+ SDNode *N = new LabelSDNode(Opcode, Root, LabelID);
+ CSEMap.InsertNode(N, IP);
+ AllNodes.push_back(N);
+ return SDOperand(N, 0);
+}
+
SDOperand SelectionDAG::getSrcValue(const Value *V) {
assert((!V || isa<PointerType>(V->getType())) &&
"SrcValue is not a pointer?");
@@ -4202,6 +4218,7 @@
void MemOperandSDNode::ANCHOR() {}
void RegisterSDNode::ANCHOR() {}
void DbgStopPointSDNode::ANCHOR() {}
+void LabelSDNode::ANCHOR() {}
void ExternalSymbolSDNode::ANCHOR() {}
void CondCodeSDNode::ANCHOR() {}
void ARG_FLAGSSDNode::ANCHOR() {}
@@ -4521,7 +4538,8 @@
case ISD::UNDEF: return "undef";
case ISD::MERGE_VALUES: return "merge_values";
case ISD::INLINEASM: return "inlineasm";
- case ISD::LABEL: return "label";
+ case ISD::DBG_LABEL: return "dbg_label";
+ case ISD::EH_LABEL: return "eh_label";
case ISD::DECLARE: return "declare";
case ISD::HANDLENODE: return "handlenode";
case ISD::FORMAL_ARGUMENTS: return "formal_arguments";
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index dc4dcc9..8751c9a 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -3179,9 +3179,7 @@
DbgRegionStartInst &RSI = cast<DbgRegionStartInst>(I);
if (MMI && RSI.getContext() && MMI->Verify(RSI.getContext())) {
unsigned LabelID = MMI->RecordRegionStart(RSI.getContext());
- DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
- DAG.getConstant(LabelID, MVT::i32),
- DAG.getConstant(0, MVT::i32)));
+ DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
}
return 0;
@@ -3191,9 +3189,7 @@
DbgRegionEndInst &REI = cast<DbgRegionEndInst>(I);
if (MMI && REI.getContext() && MMI->Verify(REI.getContext())) {
unsigned LabelID = MMI->RecordRegionEnd(REI.getContext());
- DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
- DAG.getConstant(LabelID, MVT::i32),
- DAG.getConstant(0, MVT::i32)));
+ DAG.setRoot(DAG.getLabel(ISD::DBG_LABEL, getRoot(), LabelID));
}
return 0;
@@ -3576,9 +3572,7 @@
// Both PendingLoads and PendingExports must be flushed here;
// this call might not return.
(void)getRoot();
- DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getControlRoot(),
- DAG.getConstant(BeginLabel, MVT::i32),
- DAG.getConstant(1, MVT::i32)));
+ DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getControlRoot(), BeginLabel));
}
std::pair<SDOperand,SDOperand> Result =
@@ -3595,9 +3589,7 @@
// Insert a label at the end of the invoke call to mark the try range. This
// can be used to detect deletion of the invoke via the MachineModuleInfo.
EndLabel = MMI->NextLabelID();
- DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, getRoot(),
- DAG.getConstant(EndLabel, MVT::i32),
- DAG.getConstant(1, MVT::i32)));
+ DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, getRoot(), EndLabel));
// Inform MachineModuleInfo of range.
MMI->addInvoke(LandingPad, BeginLabel, EndLabel);
@@ -5112,9 +5104,7 @@
// Add a label to mark the beginning of the landing pad. Deletion of the
// landing pad can thus be detected via the MachineModuleInfo.
unsigned LabelID = MMI->addLandingPad(BB);
- DAG.setRoot(DAG.getNode(ISD::LABEL, MVT::Other, DAG.getEntryNode(),
- DAG.getConstant(LabelID, MVT::i32),
- DAG.getConstant(1, MVT::i32)));
+ DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, DAG.getEntryNode(), LabelID));
// Mark exception register as live in.
unsigned Reg = TLI.getExceptionAddressRegister();
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
index 5c51cf7..c031191 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
@@ -144,6 +144,8 @@
Op += ":" + utostr(D->getLine());
if (D->getColumn() != 0)
Op += ":" + utostr(D->getColumn());
+ } else if (const LabelSDNode *L = dyn_cast<LabelSDNode>(Node)) {
+ Op += ": LabelID=" + utostr(L->getLabelID());
} else if (const ExternalSymbolSDNode *ES =
dyn_cast<ExternalSymbolSDNode>(Node)) {
Op += "'" + std::string(ES->getSymbol()) + "'";
diff --git a/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp b/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp
index 7f01536..842eb25 100644
--- a/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp
+++ b/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp
@@ -325,7 +325,7 @@
I != E; ++I) {
for (MachineBasicBlock::const_iterator MI = I->begin(), E = I->end();
MI != E; ++MI) {
- if (MI->getOpcode() != TargetInstrInfo::LABEL) {
+ if (!MI->isLabel()) {
MayThrow |= MI->getDesc().isCall();
continue;
}
@@ -940,7 +940,7 @@
I != E; ++I) {
for (MachineBasicBlock::const_iterator MI = I->begin(), E = I->end();
MI != E; ++MI) {
- if (MI->getOpcode() != TargetInstrInfo::LABEL) {
+ if (!MI->isLabel()) {
MayThrow |= MI->getDesc().isCall();
continue;
}
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 94ca6b0..f9f10ba 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -891,7 +891,7 @@
// If this machine instr is an inline asm, measure it.
if (MI->getOpcode() == ARM::INLINEASM)
return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
- if (MI->getOpcode() == ARM::LABEL)
+ if (MI->isLabel())
return 0;
if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
return 0;
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 3cf306a..83c3a48 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -106,7 +106,8 @@
// We don't have line number support yet.
setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
- setOperationAction(ISD::LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
// Not implemented yet.
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
diff --git a/lib/Target/CellSPU/SPURegisterInfo.cpp b/lib/Target/CellSPU/SPURegisterInfo.cpp
index d75e09e..5614896 100644
--- a/lib/Target/CellSPU/SPURegisterInfo.cpp
+++ b/lib/Target/CellSPU/SPURegisterInfo.cpp
@@ -444,7 +444,7 @@
if (hasDebugInfo) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(SPU::LABEL)).addImm(FrameLabelId).addImm(0);
+ BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(FrameLabelId);
}
// Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp)
@@ -504,7 +504,7 @@
// Mark effective beginning of when frame pointer is ready.
unsigned ReadyLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(SPU::LABEL)).addImm(ReadyLabelId).addImm(0);
+ BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(ReadyLabelId);
MachineLocation FPDst(SPU::R1);
MachineLocation FPSrc(MachineLocation::VirtualFP);
@@ -518,7 +518,7 @@
MachineBasicBlock::iterator MBBI = prior(MBB.end());
// Insert terminator label
unsigned BranchLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(SPU::LABEL)).addImm(BranchLabelId).addImm(0);
+ BuildMI(MBB, MBBI, TII.get(SPU::DBG_LABEL)).addImm(BranchLabelId);
}
}
}
diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index 69f0cb1..fa04672 100644
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -89,7 +89,8 @@
// We don't have line number support yet.
setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
- setOperationAction(ISD::LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
// IA64 has ctlz in the form of the 'fnorm' instruction. The Legalizer
// expansion for ctlz/cttz in terms of ctpop is much larger, but lower
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index a2fef46..18cedcf 100644
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -97,7 +97,8 @@
// We don't have line number support yet.
setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
- setOperationAction(ISD::LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
// Use the default for now
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
diff --git a/lib/Target/PIC16/PIC16ISelLowering.cpp b/lib/Target/PIC16/PIC16ISelLowering.cpp
index dc44e09..78936b8 100644
--- a/lib/Target/PIC16/PIC16ISelLowering.cpp
+++ b/lib/Target/PIC16/PIC16ISelLowering.cpp
@@ -135,7 +135,8 @@
// We don't have line number support yet.
setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
- setOperationAction(ISD::LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
// Use the default for now.
setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
diff --git a/lib/Target/PowerPC/PPCCodeEmitter.cpp b/lib/Target/PowerPC/PPCCodeEmitter.cpp
index 51672be..2dfdda3 100644
--- a/lib/Target/PowerPC/PPCCodeEmitter.cpp
+++ b/lib/Target/PowerPC/PPCCodeEmitter.cpp
@@ -105,7 +105,8 @@
default:
MCE.emitWordBE(getBinaryCodeForInstr(*I));
break;
- case TargetInstrInfo::LABEL:
+ case TargetInstrInfo::DBG_LABEL:
+ case TargetInstrInfo::EH_LABEL:
MCE.emitLabel(MI.getOperand(0).getImm());
break;
case TargetInstrInfo::IMPLICIT_DEF:
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index d7adea3..378fa4b 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -754,9 +754,10 @@
const char *AsmStr = MI->getOperand(0).getSymbolName();
return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
}
- case PPC::LABEL: {
+ case PPC::DBG_LABEL:
+ case PPC::EH_LABEL:
+ case PPC::GC_LABEL:
return 0;
- }
default:
return 4; // PowerPC instructions are all 4 bytes
}
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index d8ea207..7adf875 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -1068,7 +1068,7 @@
if (needsFrameMoves) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(FrameLabelId).addImm(0);
+ BuildMI(MBB, MBBI, TII.get(PPC::DBG_LABEL)).addImm(FrameLabelId);
}
// Adjust stack pointer: r1 += NegFrameSize.
@@ -1177,7 +1177,7 @@
// Mark effective beginning of when frame pointer is ready.
unsigned ReadyLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(PPC::LABEL)).addImm(ReadyLabelId).addImm(0);
+ BuildMI(MBB, MBBI, TII.get(PPC::DBG_LABEL)).addImm(ReadyLabelId);
MachineLocation FPDst(HasFP ? (IsPPC64 ? PPC::X31 : PPC::R31) :
(IsPPC64 ? PPC::X1 : PPC::R1));
diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp
index 6b0593b..cd645bf 100644
--- a/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/lib/Target/Sparc/SparcISelLowering.cpp
@@ -597,7 +597,8 @@
// We don't have line number support yet.
setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
- setOperationAction(ISD::LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
// RET must be custom lowered, to meet ABI requirements
setOperationAction(ISD::RET , MVT::Other, Custom);
@@ -616,7 +617,8 @@
// No debug info support yet.
setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
- setOperationAction(ISD::LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
setOperationAction(ISD::DECLARE, MVT::Other, Expand);
setStackPointerRegisterToSaveRestore(SP::O6);
diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index a268e16..3f897a5 100644
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -342,9 +342,23 @@
let AsmString = "";
let Namespace = "TargetInstrInfo";
}
-def LABEL : Instruction {
+def DBG_LABEL : Instruction {
let OutOperandList = (ops);
- let InOperandList = (ops i32imm:$id, i32imm:$flavor);
+ let InOperandList = (ops i32imm:$id);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+ let hasCtrlDep = 1;
+}
+def EH_LABEL : Instruction {
+ let OutOperandList = (ops);
+ let InOperandList = (ops i32imm:$id);
+ let AsmString = "";
+ let Namespace = "TargetInstrInfo";
+ let hasCtrlDep = 1;
+}
+def GC_LABEL : Instruction {
+ let OutOperandList = (ops);
+ let InOperandList = (ops i32imm:$id);
let AsmString = "";
let Namespace = "TargetInstrInfo";
let hasCtrlDep = 1;
diff --git a/lib/Target/X86/X86ATTAsmPrinter.cpp b/lib/Target/X86/X86ATTAsmPrinter.cpp
index 94cedef..aaf7d7f 100644
--- a/lib/Target/X86/X86ATTAsmPrinter.cpp
+++ b/lib/Target/X86/X86ATTAsmPrinter.cpp
@@ -272,7 +272,7 @@
for (MachineBasicBlock::const_iterator II = I->begin(), IE = I->end();
II != IE; ++II) {
// Print the assembly for the instruction.
- if (II->getOpcode() != X86::LABEL)
+ if (!II->isLabel())
hasAnyRealCode = true;
printMachineInstruction(II);
}
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index 82604a8..1b2d5ff 100644
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -490,7 +490,8 @@
case TargetInstrInfo::INLINEASM:
assert(0 && "JIT does not support inline asm!\n");
break;
- case TargetInstrInfo::LABEL:
+ case TargetInstrInfo::DBG_LABEL:
+ case TargetInstrInfo::EH_LABEL:
MCE.emitLabel(MI.getOperand(0).getImm());
break;
case TargetInstrInfo::IMPLICIT_DEF:
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index beb0b6f..6923e84 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -303,8 +303,10 @@
// FIXME - use subtarget debug flags
if (!Subtarget->isTargetDarwin() &&
!Subtarget->isTargetELF() &&
- !Subtarget->isTargetCygMing())
- setOperationAction(ISD::LABEL, MVT::Other, Expand);
+ !Subtarget->isTargetCygMing()) {
+ setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
+ setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
+ }
setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index bfc8abb..218487e 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -2681,7 +2681,8 @@
FinalSize += AI->getInlineAsmLength(AsmStr);
break;
}
- case TargetInstrInfo::LABEL:
+ case TargetInstrInfo::DBG_LABEL:
+ case TargetInstrInfo::EH_LABEL:
break;
case TargetInstrInfo::IMPLICIT_DEF:
case TargetInstrInfo::DECLARE:
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index b48cee3..1f04380 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -691,7 +691,7 @@
if (needsFrameMoves) {
// Mark effective beginning of when frame pointer becomes valid.
FrameLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId).addImm(0);
+ BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId);
}
// Update EBP with the new base value...
@@ -710,7 +710,7 @@
if (needsFrameMoves) {
// Mark effective beginning of when frame pointer is ready.
ReadyLabelId = MMI->NextLabelID();
- BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId).addImm(0);
+ BuildMI(MBB, MBBI, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId);
}
// Skip the callee-saved push instructions.