commit 44398693e767f10c1c7edea3578796f12e05af6e
author Johnny Chen <johnny.chen@apple.com> Thu Apr 15 01:20:56 2010 +0000
committer Johnny Chen <johnny.chen@apple.com> Thu Apr 15 01:20:56 2010 +0000
tree 703433cd6b00fac94f3f44c99fe2601763135206
parent 22d286b218f3267d57c507678b1af0fccc3a5df0

Wrap the error msgs in DEBUG() macro so that they won't appear in NDEBUG build.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101329 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp

diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
index 0f3a67d..b725710 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
@@ -13,8 +13,11 @@
 //
 //===----------------------------------------------------------------------===//
 
+#define DEBUG_TYPE "arm-disassembler"
+
 #include "ARMDisassemblerCore.h"
 #include "ARMAddressingModes.h"
+#include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
 /// ARMGenInstrInfo.inc - ARMGenInstrInfo.inc contains the static const
@@ -346,7 +349,7 @@
     }
     break;
   }
-  errs() << "Invalid (RegClassID, RawRegister) combination\n";
+  DEBUG(errs() << "Invalid (RegClassID, RawRegister) combination\n");
   // Encoding error.  Mark the builder with error code != 0.
   B->SetErr(-1);
   return 0;
@@ -893,7 +896,7 @@
   uint32_t msb = slice(insn, 20, 16);
   uint32_t Val = 0;
   if (msb < lsb) {
-    errs() << "Encoding error: msb < lsb\n";
+    DEBUG(errs() << "Encoding error: msb < lsb\n");
     return false;
   }
 
@@ -1911,7 +1914,7 @@
   ARM_AM::AMSubMode SubMode = getAMSubModeForBits(getPUBits(insn));
   // Must be either "ia" or "db" submode.
   if (SubMode != ARM_AM::ia && SubMode != ARM_AM::db) {
-    errs() << "Illegal addressing mode 5 sub-mode!\n";
+    DEBUG(errs() << "Illegal addressing mode 5 sub-mode!\n");
     return false;
   }
 

lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h

diff --git a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
index 4bc4070..3a6a392 100644
--- a/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
+++ b/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
@@ -1553,7 +1553,7 @@
     MI.addOperand(MCOperand::CreateImm(getLsb(insn)));
     if (Opcode == ARM::t2BFI) {
       if (getMsb(insn) < getLsb(insn)) {
-        errs() << "Encoding error: msb < lsb\n";
+        DEBUG(errs() << "Encoding error: msb < lsb\n");
         return false;
       }
       MI.addOperand(MCOperand::CreateImm(getMsb(insn) - getLsb(insn) + 1));