Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48167 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp
index e7812d4..232dc06 100644
--- a/lib/CodeGen/LowerSubregs.cpp
+++ b/lib/CodeGen/LowerSubregs.cpp
@@ -105,21 +105,32 @@
MachineFunction &MF = *MBB->getParent();
const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
- assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
- ((MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) ||
- MI->getOperand(1).isImmediate()) &&
- (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
- MI->getOperand(3).isImmediate() && "Invalid insert_subreg");
-
- unsigned DstReg = MI->getOperand(0).getReg();
+ unsigned DstReg = 0;
unsigned SrcReg = 0;
- // Check if we're inserting into an implicit value.
- if (MI->getOperand(1).isImmediate())
+ unsigned InsReg = 0;
+ unsigned SubIdx = 0;
+
+ // If only have 3 operands, then the source superreg is undef
+ // and we can supress the copy from the undef value
+ if (MI->getNumOperands() == 3) {
+ assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
+ (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
+ MI->getOperand(2).isImmediate() && "Invalid extract_subreg");
+ DstReg = MI->getOperand(0).getReg();
SrcReg = DstReg;
- else
+ InsReg = MI->getOperand(1).getReg();
+ SubIdx = MI->getOperand(2).getImm();
+ } else if (MI->getNumOperands() == 4) {
+ assert((MI->getOperand(0).isRegister() && MI->getOperand(0).isDef()) &&
+ (MI->getOperand(1).isRegister() && MI->getOperand(1).isUse()) &&
+ (MI->getOperand(2).isRegister() && MI->getOperand(2).isUse()) &&
+ MI->getOperand(3).isImmediate() && "Invalid extract_subreg");
+ DstReg = MI->getOperand(0).getReg();
SrcReg = MI->getOperand(1).getReg();
- unsigned InsReg = MI->getOperand(2).getReg();
- unsigned SubIdx = MI->getOperand(3).getImm();
+ InsReg = MI->getOperand(2).getReg();
+ SubIdx = MI->getOperand(3).getImm();
+ } else
+ assert(0 && "Malformed extract_subreg");
assert(SubIdx != 0 && "Invalid index for extract_subreg");
unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);