Add PredicateOperand to all ARM instructions that have the condition field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37066 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 79d5869..5c63921 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -524,6 +524,11 @@
return true;
}
+/// getDefaultPred - Returns a ARMCC::AL immediate node.
+static inline SDOperand getDefaultPred(SelectionDAG *CurDAG) {
+ return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
+}
+
SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
SDNode *N = Op.Val;
@@ -559,9 +564,10 @@
CPIdx,
CurDAG->getRegister(0, MVT::i32),
CurDAG->getTargetConstant(0, MVT::i32),
+ getDefaultPred(CurDAG),
CurDAG->getEntryNode()
};
- ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 4);
+ ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 5);
}
ReplaceUses(Op, SDOperand(ResNode, 0));
return NULL;
@@ -573,10 +579,14 @@
case ISD::FrameIndex: {
// Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
int FI = cast<FrameIndexSDNode>(N)->getIndex();
- unsigned Opc = Subtarget->isThumb() ? ARM::tADDrSPi : ARM::ADDri;
SDOperand TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
- return CurDAG->SelectNodeTo(N, Opc, MVT::i32, TFI,
- CurDAG->getTargetConstant(0, MVT::i32));
+ if (Subtarget->isThumb())
+ return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
+ CurDAG->getTargetConstant(0, MVT::i32));
+ else
+ return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, TFI,
+ CurDAG->getTargetConstant(0, MVT::i32),
+ getDefaultPred(CurDAG));
}
case ISD::ADD: {
// Select add sp, c to tADDhirr.
@@ -606,35 +616,39 @@
AddToISelQueue(V);
unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
- CurDAG->getTargetConstant(ShImm, MVT::i32)
+ CurDAG->getTargetConstant(ShImm, MVT::i32),
+ getDefaultPred(CurDAG)
};
- return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 5);
}
if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
SDOperand V = Op.getOperand(0);
AddToISelQueue(V);
unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
- CurDAG->getTargetConstant(ShImm, MVT::i32)
+ CurDAG->getTargetConstant(ShImm, MVT::i32),
+ getDefaultPred(CurDAG)
};
- return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 4);
+ return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 5);
}
}
break;
case ARMISD::FMRRD:
AddToISelQueue(Op.getOperand(0));
return CurDAG->getTargetNode(ARM::FMRRD, MVT::i32, MVT::i32,
- Op.getOperand(0));
+ Op.getOperand(0), getDefaultPred(CurDAG));
case ARMISD::MULHILOU:
AddToISelQueue(Op.getOperand(0));
AddToISelQueue(Op.getOperand(1));
return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32,
- Op.getOperand(0), Op.getOperand(1));
+ Op.getOperand(0), Op.getOperand(1),
+ getDefaultPred(CurDAG));
case ARMISD::MULHILOS:
AddToISelQueue(Op.getOperand(0));
AddToISelQueue(Op.getOperand(1));
return CurDAG->getTargetNode(ARM::SMULL, MVT::i32, MVT::i32,
- Op.getOperand(0), Op.getOperand(1));
+ Op.getOperand(0), Op.getOperand(1),
+ getDefaultPred(CurDAG));
case ISD::LOAD: {
LoadSDNode *LD = cast<LoadSDNode>(Op);
ISD::MemIndexedMode AM = LD->getAddressingMode();
@@ -674,9 +688,9 @@
AddToISelQueue(Chain);
AddToISelQueue(Base);
AddToISelQueue(Offset);
- SDOperand Ops[] = { Base, Offset, AMOpc, Chain };
+ SDOperand Ops[]= { Base, Offset, AMOpc, getDefaultPred(CurDAG), Chain };
return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32,
- MVT::Other, Ops, 4);
+ MVT::Other, Ops, 5);
}
}
// Other cases are autogenerated.