Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 1c00c91..73cefc4 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -552,9 +552,10 @@
KnownOne = 0;
break;
}
- case ISD::LOADX: {
+ case ISD::LOAD: {
if (ISD::isZEXTLoad(Op.Val)) {
- MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT();
+ LoadSDNode *LD = cast<LoadSDNode>(Op);
+ MVT::ValueType VT = LD->getLoadVT();
KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
}
break;
@@ -892,9 +893,10 @@
KnownOne = 0;
return;
}
- case ISD::LOADX: {
+ case ISD::LOAD: {
if (ISD::isZEXTLoad(Op.Val)) {
- MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT();
+ LoadSDNode *LD = cast<LoadSDNode>(Op);
+ MVT::ValueType VT = LD->getLoadVT();
KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask;
}
return;
@@ -1197,15 +1199,16 @@
}
// Handle LOADX separately here. EXTLOAD case will fallthrough.
- if (Op.getOpcode() == ISD::LOADX) {
- unsigned LType = Op.getConstantOperandVal(4);
- switch (LType) {
+ if (Op.getOpcode() == ISD::LOAD) {
+ LoadSDNode *LD = cast<LoadSDNode>(Op);
+ unsigned ExtType = LD->getExtensionType();
+ switch (ExtType) {
default: break;
case ISD::SEXTLOAD: // '17' bits known
- Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
+ Tmp = MVT::getSizeInBits(LD->getLoadVT());
return VTBits-Tmp+1;
case ISD::ZEXTLOAD: // '16' bits known
- Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
+ Tmp = MVT::getSizeInBits(LD->getLoadVT());
return VTBits-Tmp;
}
}