Move MRI into RegAllocBase. Clean up debug output a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121599 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/RegAllocBase.h b/lib/CodeGen/RegAllocBase.h
index 71c3faf..7d13327 100644
--- a/lib/CodeGen/RegAllocBase.h
+++ b/lib/CodeGen/RegAllocBase.h
@@ -84,6 +84,7 @@
};
const TargetRegisterInfo *TRI;
+ MachineRegisterInfo *MRI;
VirtRegMap *VRM;
LiveIntervals *LIS;
LiveUnionArray PhysReg2LiveUnion;
@@ -92,12 +93,12 @@
// query on a new live virtual register.
OwningArrayPtr<LiveIntervalUnion::Query> Queries;
- RegAllocBase(): TRI(0), VRM(0), LIS(0) {}
+ RegAllocBase(): TRI(0), MRI(0), VRM(0), LIS(0) {}
virtual ~RegAllocBase() {}
// A RegAlloc pass should call this before allocatePhysRegs.
- void init(const TargetRegisterInfo &tri, VirtRegMap &vrm, LiveIntervals &lis);
+ void init(VirtRegMap &vrm, LiveIntervals &lis);
// Get an initialized query to check interferences between lvr and preg. Note
// that Query::init must be called at least once for each physical register
diff --git a/lib/CodeGen/RegAllocBasic.cpp b/lib/CodeGen/RegAllocBasic.cpp
index 753688b..3c84543 100644
--- a/lib/CodeGen/RegAllocBasic.cpp
+++ b/lib/CodeGen/RegAllocBasic.cpp
@@ -74,9 +74,6 @@
{
// context
MachineFunction *MF;
- const TargetMachine *TM;
- MachineRegisterInfo *MRI;
-
BitVector ReservedRegs;
// analyses
@@ -206,9 +203,9 @@
new(Array + r) LiveIntervalUnion(r, allocator);
}
-void RegAllocBase::init(const TargetRegisterInfo &tri, VirtRegMap &vrm,
- LiveIntervals &lis) {
- TRI = &tri;
+void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis) {
+ TRI = &vrm.getTargetRegInfo();
+ MRI = &vrm.getRegInfo();
VRM = &vrm;
LIS = &lis;
PhysReg2LiveUnion.init(UnionAllocator, TRI->getNumRegs());
@@ -262,13 +259,15 @@
// selectOrSplit requests the allocator to return an available physical
// register if possible and populate a list of new live intervals that
// result from splitting.
+ DEBUG(dbgs() << "\nselectOrSplit " << MRI->getRegClass(VirtReg.reg)->getName()
+ << ':' << VirtReg << '\n');
typedef SmallVector<LiveInterval*, 4> VirtRegVec;
VirtRegVec SplitVRegs;
unsigned AvailablePhysReg = selectOrSplit(VirtReg, SplitVRegs);
if (AvailablePhysReg) {
- DEBUG(dbgs() << "allocating: " << TRI->getName(AvailablePhysReg) <<
- " " << VirtReg << '\n');
+ DEBUG(dbgs() << "allocating: " << TRI->getName(AvailablePhysReg)
+ << " for " << VirtReg << '\n');
assert(!VRM->hasPhys(VirtReg.reg) && "duplicate vreg in union");
VRM->assignVirt2Phys(VirtReg.reg, AvailablePhysReg);
PhysReg2LiveUnion[AvailablePhysReg].unify(VirtReg);
@@ -416,7 +415,6 @@
// Check for an available register in this class.
const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
- DEBUG(dbgs() << "RegClass: " << TRC->getName() << ' ');
for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF),
E = TRC->allocation_order_end(*MF);
@@ -469,14 +467,9 @@
<< ((Value*)mf.getFunction())->getName() << '\n');
MF = &mf;
- TM = &mf.getTarget();
- MRI = &mf.getRegInfo();
-
DEBUG(RMF = &getAnalysis<RenderMachineFunction>());
- const TargetRegisterInfo *TRI = TM->getRegisterInfo();
- RegAllocBase::init(*TRI, getAnalysis<VirtRegMap>(),
- getAnalysis<LiveIntervals>());
+ RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
ReservedRegs = TRI->getReservedRegs(*MF);
diff --git a/lib/CodeGen/RegAllocGreedy.cpp b/lib/CodeGen/RegAllocGreedy.cpp
index af2c55e..01946c0 100644
--- a/lib/CodeGen/RegAllocGreedy.cpp
+++ b/lib/CodeGen/RegAllocGreedy.cpp
@@ -45,9 +45,6 @@
class RAGreedy : public MachineFunctionPass, public RegAllocBase {
// context
MachineFunction *MF;
- const TargetMachine *TM;
- MachineRegisterInfo *MRI;
-
BitVector ReservedRegs;
// analyses
@@ -230,11 +227,6 @@
SmallVector<unsigned, 8> PhysRegSpillCands, ReassignCands;
// Check for an available register in this class.
- DEBUG({
- const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg);
- dbgs() << "RegClass: " << TRC->getName() << ' ';
- });
-
AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs);
while (unsigned PhysReg = Order.next()) {
// Check interference and as a side effect, intialize queries for this
@@ -305,12 +297,7 @@
<< ((Value*)mf.getFunction())->getName() << '\n');
MF = &mf;
- TM = &mf.getTarget();
- MRI = &mf.getRegInfo();
-
- const TargetRegisterInfo *TRI = TM->getRegisterInfo();
- RegAllocBase::init(*TRI, getAnalysis<VirtRegMap>(),
- getAnalysis<LiveIntervals>());
+ RegAllocBase::init(getAnalysis<VirtRegMap>(), getAnalysis<LiveIntervals>());
ReservedRegs = TRI->getReservedRegs(*MF);
SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM));