TableGen subtarget parser. Handle new machine model.
Collect SchedClasses and SchedRW types from the subtarget defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163951 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp
index 5dfd716..2fdd930 100644
--- a/utils/TableGen/SubtargetEmitter.cpp
+++ b/utils/TableGen/SubtargetEmitter.cpp
@@ -521,7 +521,7 @@
std::vector<std::vector<InstrItinerary> >::iterator
ProcItinListsIter = ProcItinLists.begin();
for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
- PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
+ PE = SchedModels.procModelEnd(); PI != PE; ++PI, ++ProcItinListsIter) {
Record *ItinsDef = PI->ItinsDef;
if (!ItinsDefSet.insert(ItinsDef))
@@ -532,7 +532,7 @@
// Get the itinerary list for the processor.
assert(ProcItinListsIter != ProcItinLists.end() && "bad iterator");
- std::vector<InstrItinerary> &ItinList = *ProcItinListsIter++;
+ std::vector<InstrItinerary> &ItinList = *ProcItinListsIter;
OS << "\n";
OS << "static const llvm::InstrItinerary ";
@@ -621,7 +621,7 @@
const std::string &Name = Processor->getValueAsString("Name");
const std::string &ProcModelName =
- SchedModels.getProcModel(Processor).ModelName;
+ SchedModels.getModelForProc(Processor).ModelName;
// Emit as { "cpu", procinit },
OS << " { "