commit 48e9f26df5f6085a1c972069ba6aa227821cd41c
author Brian Gaeke <gaeke@uiuc.edu> Sat Jan 24 09:23:46 2004 +0000
committer Brian Gaeke <gaeke@uiuc.edu> Sat Jan 24 09:23:46 2004 +0000
tree 730c837a3edc4428ed4df6126f6b23f4317e1db5
parent 79b0c3f0b9d91bbda354a2c6f22b6578655a5143

Fix a couple of places I noticed where "X86" was hard-coded.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10974 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/InstrSelectorEmitter.cpp

diff --git a/utils/TableGen/InstrSelectorEmitter.cpp b/utils/TableGen/InstrSelectorEmitter.cpp
index dc5dbf2..5c09393 100644
--- a/utils/TableGen/InstrSelectorEmitter.cpp
+++ b/utils/TableGen/InstrSelectorEmitter.cpp
@@ -1023,7 +1023,7 @@
      << "  class " << Target.getName() << "ISel {\n"
      << "    SelectionDAG &DAG;\n"
      << "  public:\n"
-     << "    X86ISel(SelectionDAG &D) : DAG(D) {}\n"
+     << "    " << Target.getName () << "ISel(SelectionDAG &D) : DAG(D) {}\n"
      << "    void generateCode();\n"
      << "  private:\n"
      << "    unsigned makeAnotherReg(const TargetRegisterClass *RC) {\n"
@@ -1060,7 +1060,7 @@
   OS << "  };\n}\n\n";
 
   // Emit the generateCode entry-point...
-  OS << "void X86ISel::generateCode() {\n"
+  OS << "void " << Target.getName () << "ISel::generateCode() {\n"
      << "  SelectionDAGNode *Root = DAG.getRoot();\n"
      << "  assert(Root->getValueType() == MVT::isVoid && "
                                        "\"Root of DAG produces value??\");\n\n"