commit 4903c15b7d92802a4f0f28928a89bb4c0d5e212f
author Andrew Trick <atrick@apple.com> Thu Oct 11 05:37:06 2012 +0000
committer Andrew Trick <atrick@apple.com> Thu Oct 11 05:37:06 2012 +0000
tree e7e0717dabf441ae68c8e454639a855f86542dcd
parent 5e01f80bf85b9a68352d4c146caa9ddcf6af6dcf

misched: Handle "transient" non-instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165701 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/TargetInstrInfoImpl.cpp

diff --git a/lib/CodeGen/TargetInstrInfoImpl.cpp b/lib/CodeGen/TargetInstrInfoImpl.cpp
index 8ed66f7..4439192 100644
--- a/lib/CodeGen/TargetInstrInfoImpl.cpp
+++ b/lib/CodeGen/TargetInstrInfoImpl.cpp
@@ -563,6 +563,8 @@
 /// Return the default expected latency for a def based on it's opcode.
 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel *SchedModel,
                                             const MachineInstr *DefMI) const {
+  if (DefMI->isTransient())
+    return 0;
   if (DefMI->mayLoad())
     return SchedModel->LoadLatency;
   if (isHighLatencyDef(DefMI->getOpcode()))