misched: Handle "transient" non-instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165701 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/TargetSchedule.cpp b/lib/CodeGen/TargetSchedule.cpp
index 4e753c6..7a6e260 100644
--- a/lib/CodeGen/TargetSchedule.cpp
+++ b/lib/CodeGen/TargetSchedule.cpp
@@ -50,10 +50,12 @@
int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
return (UOps >= 0) ? UOps : TII->getNumMicroOps(&InstrItins, MI);
}
- if (hasInstrSchedModel())
- return resolveSchedClass(MI)->NumMicroOps;
-
- return 1;
+ if (hasInstrSchedModel()) {
+ const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
+ if (SCDesc->isValid())
+ return SCDesc->NumMicroOps;
+ }
+ return MI->isTransient() ? 0 : 1;
}
/// If we can determine the operand latency from the def only, without machine
@@ -199,7 +201,7 @@
report_fatal_error(ss.str());
}
#endif
- return 1;
+ return DefMI->isTransient() ? 0 : 1;
}
unsigned TargetSchedModel::computeInstrLatency(const MachineInstr *MI) const {
@@ -209,16 +211,18 @@
return TII->getInstrLatency(&InstrItins, MI);
if (hasInstrSchedModel()) {
- unsigned Latency = 0;
const MCSchedClassDesc *SCDesc = resolveSchedClass(MI);
- for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
- DefIdx != DefEnd; ++DefIdx) {
- // Lookup the definition's write latency in SubtargetInfo.
- const MCWriteLatencyEntry *WLEntry =
- STI->getWriteLatencyEntry(SCDesc, DefIdx);
- Latency = std::max(Latency, WLEntry->Cycles);
+ if (SCDesc->isValid()) {
+ unsigned Latency = 0;
+ for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries;
+ DefIdx != DefEnd; ++DefIdx) {
+ // Lookup the definition's write latency in SubtargetInfo.
+ const MCWriteLatencyEntry *WLEntry =
+ STI->getWriteLatencyEntry(SCDesc, DefIdx);
+ Latency = std::max(Latency, WLEntry->Cycles);
+ }
+ return Latency;
}
- return Latency;
}
return TII->defaultDefLatency(&SchedModel, MI);
}
@@ -251,10 +255,12 @@
// an unbuffered resource. If so, it treated like an in-order cpu.
if (hasInstrSchedModel()) {
const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI);
- for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
- *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) {
- if (!SchedModel.getProcResource(PRI->ProcResourceIdx)->IsBuffered)
- return 1;
+ if (SCDesc->isValid()) {
+ for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
+ *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI) {
+ if (!SchedModel.getProcResource(PRI->ProcResourceIdx)->IsBuffered)
+ return 1;
+ }
}
}
return 0;