ret 0; works, not much else
still lots of uglyness.
Maybe calls will come soon.
Fixing the return value of things will be necessary to make alpha work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23832 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaTargetMachine.cpp b/lib/Target/Alpha/AlphaTargetMachine.cpp
index 8f26329..37f71b2 100644
--- a/lib/Target/Alpha/AlphaTargetMachine.cpp
+++ b/lib/Target/Alpha/AlphaTargetMachine.cpp
@@ -32,6 +32,9 @@
cl::opt<bool> EnableAlphaLSR("enable-lsr-for-alpha",
cl::desc("Enable LSR for Alpha (beta option!)"),
cl::Hidden);
+ cl::opt<bool> EnableAlphaDAG("enable-dag-isel-for-alpha",
+ cl::desc("Enable DAG ISEL for Alpha (beta option!)"),
+ cl::Hidden);
}
unsigned AlphaTargetMachine::getModuleMatchQuality(const Module &M) {
@@ -94,7 +97,10 @@
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
- PM.add(createAlphaPatternInstructionSelector(*this));
+ if (EnableAlphaDAG)
+ PM.add(createAlphaISelDag(*this));
+ else
+ PM.add(createAlphaPatternInstructionSelector(*this));
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(&std::cerr));