diff --git a/lib/Target/SystemZ/SystemZInstrFP.td b/lib/Target/SystemZ/SystemZInstrFP.td
index 390104c..9e367fe 100644
--- a/lib/Target/SystemZ/SystemZInstrFP.td
+++ b/lib/Target/SystemZ/SystemZInstrFP.td
@@ -277,20 +277,20 @@
                           (implicit PSW)]>;
 
 def FCONVGR32   : Pseudo<(outs GR32:$dst), (ins FP32:$src),
-                         "cfebr\t{$dst, $src}",
+                         "cfebr\t{$dst, 5, $src}",
                          [(set GR32:$dst, (fp_to_sint FP32:$src)),
                           (implicit PSW)]>;
 def FCONVGR32r64: Pseudo<(outs GR32:$dst), (ins FP64:$src),
-                         "cgebr\t{$dst, $src}",
+                         "cgebr\t{$dst, 5, $src}",
                          [(set GR32:$dst, (fp_to_sint FP64:$src)),
                           (implicit PSW)]>;
 
 def FCONVGR64r32: Pseudo<(outs GR64:$dst), (ins FP32:$src),
-                         "cfdbr\t{$dst, $src}",
+                         "cfdbr\t{$dst, 5, $src}",
                          [(set GR64:$dst, (fp_to_sint FP32:$src)),
                           (implicit PSW)]>;
 def FCONVGR64   : Pseudo<(outs GR64:$dst), (ins FP64:$src),
-                         "cgdbr\t{$dst, $src}",
+                         "cgdbr\t{$dst, 5, $src}",
                          [(set GR64:$dst, (fp_to_sint FP64:$src)),
                           (implicit PSW)]>;
 } // Defs = [PSW]